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* Add support for musl-libc on ARM Linux.Rafael Espindola2016-06-244-5/+17
| | | | | | Patch by Lei Zhang! llvm-svn: 273726
* [ARM] Remove dead SDNodes. NFC.Ahmed Bougacha2016-06-241-7/+0
| | | | | | The opcodes are used, but only by DAG->DAG. llvm-svn: 273717
* [X86] Remove dead ISD opcodes. NFC.Ahmed Bougacha2016-06-245-18/+0
| | | | llvm-svn: 273716
* [AArch64] Adjust the model for the vector by element FP multiplies on Exynos ↵Evandro Menezes2016-06-241-4/+4
| | | | | | M1. (NFC) llvm-svn: 273708
* Use existing predicate. NFC.Rafael Espindola2016-06-241-5/+1
| | | | | | This doesn't handle ELF, but neither did the previous code. llvm-svn: 273677
* Merge two identical if branches. NFC.Rafael Espindola2016-06-241-14/+11
| | | | llvm-svn: 273674
* Merge two identical if branches. NFC.Rafael Espindola2016-06-241-11/+3
| | | | llvm-svn: 273673
* clang-format a region. NFC.Rafael Espindola2016-06-241-4/+4
| | | | llvm-svn: 273672
* AMDGPU: Add stub custom CodeGenPrepare passMatt Arsenault2016-06-244-0/+88
| | | | | | | | This will do various things including ones CodeGenPrepare does, but with knowledge of uniform values. llvm-svn: 273657
* AMDGPU: Remove disable-irstructurizer subtarget featureMatt Arsenault2016-06-244-14/+7
| | | | | | | | The only real reason to use it is for testing, so replace it with a command line option instead of a potentially function dependent feature. llvm-svn: 273653
* AMDGPU: Cleanup subtarget handling.Matt Arsenault2016-06-2458-706/+879
| | | | | | | | | Split AMDGPUSubtarget into amdgcn/r600 specific subclasses. This removes most of the static_casting of the basic codegen classes everywhere, and tries to restrict the features visible on the wrong target. llvm-svn: 273652
* Switch more loops to be range-basedDavid Majnemer2016-06-242-4/+3
| | | | | | | This makes the code a little more concise, no functional change is intended. llvm-svn: 273644
* [X86] Combine two nearby calls to isSingleInputShuffleVector. NFCCraig Topper2016-06-241-6/+4
| | | | llvm-svn: 273643
* [ARM] Use aapcs_vfp for ___truncdfhf2 on v7k.Ahmed Bougacha2016-06-241-11/+13
| | | | | | | r215348 overrode the f16 libcalls to be soft-float, but v7k uses the default (hard-float) calling convention. llvm-svn: 273631
* [AArch64] Model the cost of vector by element FP multiplies on Exynos M1. (NFC)Evandro Menezes2016-06-231-0/+6
| | | | llvm-svn: 273630
* Support/ELF: Add R_AMDGPU_GOTPCREL relocationTom Stellard2016-06-231-0/+7
| | | | | | | | | | | | | Summary: We will start generating this in a future patch. Reviewers: arsenm, kzhuravl, rafael, ruiu, tony-tye Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21482 llvm-svn: 273628
* Codegen: [X86] preservere memory refs for folded umul_lohiKyle Butt2016-06-231-2/+10
| | | | | | | | | Memory references were not being propagated for this folded load. This prevented optimizations like LICM from hoisting the load. Added test to verify that this allows LICM to proceed. llvm-svn: 273617
* Uses shouldAssumeDSOLocal.Rafael Espindola2016-06-231-10/+2
| | | | | | With that SystemZ knows to avoid a GOT for PIE. llvm-svn: 273614
* Refactor to use shouldAssumeDSOLocal. NFC.Rafael Espindola2016-06-231-10/+14
| | | | llvm-svn: 273612
* AMDGPU: Add option to disable spilling SGPRs to VGPRs.Matt Arsenault2016-06-231-2/+9
| | | | | | This can help debug spilling problems. llvm-svn: 273605
* Refactor duplicated code. NFC.Rafael Espindola2016-06-231-20/+17
| | | | llvm-svn: 273595
* [X86] Extract HiPE prologue constants into metadataMichael Kuperstein2016-06-231-3/+31
| | | | | | | | | | | | | | | | | | | | | | X86FrameLowering::adjustForHiPEPrologue() contains a hard-coded offset into an Erlang Runtime System-internal data structure (the PCB). As the layout of this data structure is prone to change, this poses problems for maintaining compatibility. To address this problem, the compiler can produce this information as module-level named metadata. For example (where P_NSP_LIMIT is the offending offset): !hipe.literals = !{ !2, !3, !4 } !2 = !{ !"P_NSP_LIMIT", i32 152 } !3 = !{ !"X86_LEAF_WORDS", i32 24 } !4 = !{ !"AMD64_LEAF_WORDS", i32 24 } Patch by Magnus Lang Differential Revision: http://reviews.llvm.org/D20363 llvm-svn: 273593
* Fix the wasm build by including EndianStream.hReid Kleckner2016-06-231-0/+1
| | | | llvm-svn: 273591
* Preserve DebugInfo when replacing values in DAGCombinerNirav Dave2016-06-232-4/+2
| | | | | | | | | | | | | | | | | | | | | Recommiting after correcting over-eager Debug Value transfer fixing PR28270. [DAG] Previously debug values would transfer debuginfo for the selected start node for a replacement which allows for debug to be dropped. Push debug value transfer to occur with node/value replacement in SelectionDAG, remove now extraneous transfers of debug values. This refixes PR9817 which was being incompletely checked in the testsuite. Reviewers: jyknight Subscribers: dblaikie, llvm-commits Differential Revision: http://reviews.llvm.org/D21037 llvm-svn: 273585
* [ARM] Lower (select_cc k k (select_cc ~k ~k x)) into (SSAT l_k x)Pablo Barrio2016-06-234-1/+141
| | | | | | | | | | | | | | | | | Summary: SSAT saturates an integer, making sure that its value lies within an interval [-k, k]. Since the constant is given to SSAT as the number of bytes set to one, k + 1 must be a power of 2, otherwise the optimization is not possible. Also, the select_cc must use < and > respectively so that they define an interval. Reviewers: mcrosier, jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D21372 llvm-svn: 273581
* Revert r273567 "[SystemZ] Let z13 also support FeatureMiscellaneousExtensions."Hans Wennborg2016-06-231-1/+0
| | | | | | It broke test/CodeGen/SystemZ/vec-extract-02.ll llvm-svn: 273575
* [SystemZ] Let z13 also support FeatureMiscellaneousExtensions.Jonas Paulsson2016-06-231-0/+1
| | | | | | | | | This processor feature had been left out by mistake from the z13 ProcessorModel. Reviewed by Ulrich Weigand. llvm-svn: 273567
* [AMDGPU] Enable absolute expression initializer for amd_kernel_code_t fields.Valery Pykhtin2016-06-234-23/+26
| | | | | | Differential Revision: http://reviews.llvm.org/D21380 llvm-svn: 273561
* [mips] Don't derive the default ABI from the CPU in the backend.Daniel Sanders2016-06-231-28/+3
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The backend has no reason to behave like a driver and should generally do as it's told (and error out if it can't) instead of trying to figure out what the API user meant. The default ABI is still derived from the arch component as a concession to backwards compatibility. API-users that previously passed an explicit CPU and a triple that was inconsistent with the CPU (e.g. mips-linux-gnu and mips64r2) may get a different ABI to what they got before. However, it's expected that there are no such users on the basis that CodeGen has been asserting that the triple is consistent with the selected ABI for several releases. API-users that were consistent or passed '' or 'generic' as the CPU will see no difference. Reviewers: sdardis, rafael Subscribers: rafael, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21466 llvm-svn: 273557
* [ARM] Use member initializers in ARMSubtarget. NFCIDiana Picus2016-06-231-66/+22
| | | | | | | | | Move most of the initializations in ARMSubtarget::initializeEnvironment to member initializers. Change suggested by Matthias Braun (see http://reviews.llvm.org/D21432). llvm-svn: 273556
* [mips][ias] Integers are not registers.Daniel Sanders2016-06-231-6/+0
| | | | | | | | | | | | | | | | | | | Summary: When parseAnyRegister() encounters a symbol alias, it parses integers and adds a corresponding expression to the operand list. This is clearly wrong since the only operands that parseAnyRegister() should be accepting are registers. It's not clear why this code was added and there are no test cases that cover it. I think it might be leftover from when searchSymbolAlias() was more widely used. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21377 llvm-svn: 273555
* [AMDGPU] Remove exit-on-error in test (PR27761)Diana Picus2016-06-232-2/+5
| | | | | | | | | | | | | | | | | The exit-on-error flag was necessary in order to avoid an assertion when handling DYNAMIC_STACKALLOC nodes in SelectionDAGLegalize. We can avoid the assertion by creating some dummy nodes. This enables us to remove the exit-on-error flag on the first 2 run lines (SI), but on the third run line (R600) we would run into another assertion when trying to reserve indirect registers. This patch also replaces that assertion with an early exit from the function. Fixes PR27761. Differential Revision: http://reviews.llvm.org/D20852 llvm-svn: 273550
* [mips] Fix dext/dins definitionsSimon Dardis2016-06-231-6/+8
| | | | | | | | | | | dext and dins, along with their 'm' and 'u' variants are defined in mips64r2, not mips64. Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D21608 llvm-svn: 273549
* [ARM] Do not test for CPUs, use SubtargetFeatures (Part 1). NFCIDiana Picus2016-06-236-25/+91
| | | | | | | | | | | | | This is a cleanup commit similar to r271555, but for ARM. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. Since the ARM backend seems to have quite a lot of calls to these methods, I intend to submit 5-6 subtarget features at a time, instead of one big lump. Differential Revision: http://reviews.llvm.org/D21432 llvm-svn: 273544
* [AVX512] Remove masked unpack intrinsics and autoupgrade to vectorshuffle ↵Craig Topper2016-06-232-72/+10
| | | | | | and selects. llvm-svn: 273543
* [X86] Add assert to ensure only 128-bit vector types are used. 256 or ↵Craig Topper2016-06-231-0/+2
| | | | | | 512-bit would require lane handling which is missing. llvm-svn: 273542
* Use C++ comments for large block comment.Eric Christopher2016-06-231-16/+17
| | | | llvm-svn: 273526
* AMDGPU: readlane/writelane do not read execMatt Arsenault2016-06-232-2/+26
| | | | llvm-svn: 273525
* Revert r273456, "Preserve DebugInfo when replacing values in DAGCombiner" as ↵Peter Collingbourne2016-06-232-2/+4
| | | | | | it caused pr28270. llvm-svn: 273518
* [codeview] Add EFLAGS to the list of CodeView register numbersReid Kleckner2016-06-221-1/+3
| | | | llvm-svn: 273516
* AMDGPU: Fix liveness when expanding m0 loopMatt Arsenault2016-06-222-23/+67
| | | | llvm-svn: 273514
* Prune some includes from headers and sink some inline functionsReid Kleckner2016-06-224-0/+4
| | | | | | | | MCSymbol.h shouldn't pull in MCAssembler.h, just MCFragment.h. MCLinkerOptimizationHint.h shouldn't need MCMachObjectWriter.h. The rest is fixing the fallout. llvm-svn: 273507
* Use shouldAssumeDSOLocal.Rafael Espindola2016-06-221-5/+5
| | | | | | With this it handle -fPIE. llvm-svn: 273499
* Extract a few variables to make 'if' smaller. NFC.Rafael Espindola2016-06-221-7/+8
| | | | llvm-svn: 273497
* AMDGPU/SI: Define an intrinsic to expose ds_swizzle_b32Changpeng Fang2016-06-221-0/+12
| | | | | | | | Reviewers: tstellarAMD, arsenm Differential Revision: http://reviews.llvm.org/D21533 llvm-svn: 273496
* AMDGPU: Run verifier after 2nd run of SIShrinkInstructionsMatt Arsenault2016-06-221-1/+1
| | | | llvm-svn: 273469
* AMDGPU: Fix verifier errors in SILowerControlFlowMatt Arsenault2016-06-2210-133/+217
| | | | | | | | | | | | | The main sin this was committing was using terminator instructions in the middle of the block, and then not updating the block successors / predecessors. Split the blocks up to avoid this and introduce new pseudo instructions for branches taken with exec masking. Also use a pseudo instead of emitting s_endpgm and erasing it in the special case of a non-void return. llvm-svn: 273467
* [Hexagon] Add SDAG preprocessing step to expose shifted addressing modesKrzysztof Parzyszek2016-06-221-1/+54
| | | | | | | | | | | Transform: (store ch addr (add x (add (shl y c) e))) to: (store ch addr (add x (shl (add y d) c))), where e = (shl d c) for some integer d. The purpose of this is to enable generation of loads/stores with shifted addressing mode, i.e. mem(x+y<<#c). For that, the shift value c must be 0, 1 or 2. llvm-svn: 273466
* [AArch64] Remove an overly aggressive assert.Chad Rosier2016-06-221-5/+0
| | | | llvm-svn: 273458
* Start using shouldAssumeDSOLocal on Hexagon.Rafael Espindola2016-06-221-2/+3
| | | | | | | Include a token test showing that access to private is now the same as to internal. llvm-svn: 273457
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