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* remove the rest of hte owningptr's, no functionality change.Chris Lattner2010-10-281-57/+59
| | | | llvm-svn: 117603
* Reduce malloc thrashing.Benjamin Kramer2010-10-281-1/+1
| | | | llvm-svn: 117572
* PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.Jim Grosbach2010-10-284-20/+44
| | | | llvm-svn: 117571
* rearrange ParseRegisterList.Chris Lattner2010-10-281-16/+30
| | | | llvm-svn: 117560
* refactor some code to simplify it, eliminating some owningptr's.Chris Lattner2010-10-281-65/+60
| | | | llvm-svn: 117559
* Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng2010-10-284-23/+85
| | | | llvm-svn: 117531
* Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ↵Evan Cheng2010-10-284-85/+23
| | | | | | to fail. Ugh. llvm-svn: 117520
* - Assign load / store with shifter op address modes the right itinerary classes.Evan Cheng2010-10-284-23/+85
| | | | | | | | | | - For now, loads of [r, r] addressing mode is the same as the [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should identify the former case and reduce the output latency by 1. - Also identify [r, r << 2] case. This special form of shifter addressing mode is "free". llvm-svn: 117519
* Fix pastos in handling of AVX cvttsd2si, PR8491.Dale Johannesen2010-10-281-4/+4
| | | | | | | Bruno, please review, but I'm pretty sure this is right. Patch by Alex Mac! llvm-svn: 117514
* Add correct NEON encodings for vtbl and vtbx.Owen Anderson2010-10-281-29/+29
| | | | llvm-svn: 117513
* Add correct NEON encodings for vext, vtrn, vuzp, and vzip.Owen Anderson2010-10-271-2/+8
| | | | llvm-svn: 117512
* Fix compiler warnings about signed/unsigned comparisons.Bob Wilson2010-10-271-2/+2
| | | | llvm-svn: 117511
* Shifter ops are not always free. Do not fold them (especially to formEvan Cheng2010-10-272-16/+119
| | | | | | | complex load / store addressing mode) when they have higher cost and when they have more than one use. llvm-svn: 117509
* Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach2010-10-279-101/+94
| | | | | | | | the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505
* Provide correct encodings for NEON vcvt, which has its own special immediate ↵Owen Anderson2010-10-274-6/+16
| | | | | | | | encoding for specifying fractional bits for fixed point conversions. llvm-svn: 117501
* Trailing whitespaceJim Grosbach2010-10-271-17/+17
| | | | llvm-svn: 117496
* Provide correct encodings for the get_lane and set_lane variants of vmov.Owen Anderson2010-10-272-41/+64
| | | | llvm-svn: 117495
* Added the x86 instruction ud2b (2nd official undefined instruction).Kevin Enderby2010-10-271-1/+3
| | | | llvm-svn: 117485
* JIT imm12 encoding for constant pool entry references.Jim Grosbach2010-10-271-0/+4
| | | | llvm-svn: 117483
* SelectionDAG shuffle nodes do not allow operands with different numbers ofBob Wilson2010-10-271-0/+55
| | | | | | | | | | | | | | | | | | | elements than the result vector type. So, when an instruction like: %8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2> is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is: shuffle [a,b], [c,d] is changed to: shuffle [a,b,u,u], [c,d,u,u] That's probably the right thing for x86 but for NEON, we'd much rather have: shuffle [a,b,c,d], undef Teach the DAG combiner how to do that transformation for ARM. Radar 8597007. llvm-svn: 117482
* ARM JIT fix for LDRi12 and company.Jim Grosbach2010-10-272-4/+18
| | | | llvm-svn: 117478
* Provide correct NEON encodings for vdup.Owen Anderson2010-10-272-8/+42
| | | | llvm-svn: 117475
* x86-Win32: Switch ftol2 calling convention from stdcall to C.Michael J. Spencer2010-10-271-2/+2
| | | | llvm-svn: 117474
* The new LDR* instruction patterns should handle the necessary encoding ofJim Grosbach2010-10-271-0/+7
| | | | | | | operands in the TableGen'erated bits, so we don't need to do the additional magic explicitly. llvm-svn: 117461
* Add correct NEON encodings for vsli and vsri.Owen Anderson2010-10-271-8/+8
| | | | llvm-svn: 117459
* Add correct NEON encodings for vsra and vrsra.Owen Anderson2010-10-271-10/+10
| | | | llvm-svn: 117458
* The immediate operands of an LDRi12 instruction doesn't need the addrmode2Jim Grosbach2010-10-271-2/+6
| | | | | | encoding tricks. Handle the 'imm doesn't fit in the insn' case. llvm-svn: 117454
* Yet another tweak to X86 instructions to add ud2a as an alias to ud2Kevin Enderby2010-10-271-0/+1
| | | | | | (still to add ud2b). llvm-svn: 117435
* Another tweak to X86 instructions to add the missing flex instruction (withoutKevin Enderby2010-10-271-1/+2
| | | | | | the wait prefix). llvm-svn: 117434
* Tweaks to X86 instructions to allow the 'w' suffix in places it makesKevin Enderby2010-10-271-0/+6
| | | | | | | | | sense, when the instruction takes the 16-bit ax register or m16 memory location. These changes to llvm-mc matches what the darwin assembler allows for these instructions. Done differently than in r117031 that caused a valgrind error which was later reverted. llvm-svn: 117433
* LDRi12 machine instructions handle negative offset operands normally (simpleJim Grosbach2010-10-272-4/+14
| | | | | | integer values), not with the addrmode2 encoding. llvm-svn: 117429
* Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mcKevin Enderby2010-10-271-1/+14
| | | | | | | will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. llvm-svn: 117427
* One more spot where the new arm mode LDR instruction representationJim Grosbach2010-10-271-3/+3
| | | | | | | doesn't need the additional addrmode2 register operand. Missed it the first time around. llvm-svn: 117421
* Adding disassembler to the MicroBlaze backend.Wesley Peck2010-10-2717-121/+886
| | | | llvm-svn: 117420
* Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing onJim Grosbach2010-10-276-17/+18
| | | | | | rdar://8477752. llvm-svn: 117419
* Since I parameterized this bit, I should probably actually use said parameter.Jim Grosbach2010-10-261-2/+2
| | | | llvm-svn: 117418
* Use a MemIntrinsicSDNode for ISD::PREFETCH, which touchesDale Johannesen2010-10-261-1/+0
| | | | | | | | memory, so a MachineMemOperand is useful (not propagated into the MachineInstr yet). No functional change except for dump output. llvm-svn: 117413
* Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and ↵Owen Anderson2010-10-261-8/+8
| | | | | | vqrshrun. llvm-svn: 117411
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-2614-65/+314
| | | | | | | | explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
* Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.Owen Anderson2010-10-261-4/+4
| | | | llvm-svn: 117402
* Simplify classes for shift instructions, which are never commutable.Owen Anderson2010-10-261-19/+19
| | | | llvm-svn: 117398
* Provide correct NEON encodings for vshl, register and immediate forms.Owen Anderson2010-10-262-2/+81
| | | | llvm-svn: 117394
* Grammar.Jim Grosbach2010-10-261-1/+1
| | | | llvm-svn: 117388
* Nuke extraneous comment. It's applicable elsewhere, but not in this func.Jim Grosbach2010-10-261-2/+0
| | | | llvm-svn: 117387
* Add correct NEON encoding for vpadal.Owen Anderson2010-10-261-6/+6
| | | | llvm-svn: 117380
* handle X86::EH_RETURN64 and X86::EH_RETURN.Rafael Espindola2010-10-261-0/+17
| | | | llvm-svn: 117378
* Add NEON encodings for vmov and vmvn of immediates.Owen Anderson2010-10-262-12/+40
| | | | llvm-svn: 117374
* Implement some relaxations for arithmetic instructions. The limitationRafael Espindola2010-10-261-12/+92
| | | | | | | on RIP relative relocations looks artificial, but this is a superset of what we were able to do before. llvm-svn: 117364
* Change v64 datalayout in SPU.Kalle Raiskila2010-10-261-1/+1
| | | | | | | | | | | | | | The SPU ABI does not mention v64, and all examples in C suggest v128 are treated similarily to arrays, we use array alignment for v64 too. This makes the alignment of e.g. [2 x <2 x i32>] behave "intuitively" and similar to as if the elements were e.g. i32s. This also makes an "unaligned store" test to be aligned, with different (but functionally equivalent) code generated. llvm-svn: 117360
* Use instruction itinerary to determine what instructions are 'cheap'.Evan Cheng2010-10-263-0/+27
| | | | llvm-svn: 117348
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