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* Micro-optimization:Bill Wendling2010-03-051-13/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code: float floatingPointComparison(float x, float y) { double product = (double)x * y; if (product == 0.0) return product; return product - 1.0; } produces this: _floatingPointComparison: 0000000000000000 cvtss2sd %xmm1,%xmm1 0000000000000004 cvtss2sd %xmm0,%xmm0 0000000000000008 mulsd %xmm1,%xmm0 000000000000000c pxor %xmm1,%xmm1 0000000000000010 ucomisd %xmm1,%xmm0 0000000000000014 jne 0x00000004 0000000000000016 jp 0x00000002 0000000000000018 jmp 0x00000008 000000000000001a addsd 0x00000006(%rip),%xmm0 0000000000000022 cvtsd2ss %xmm0,%xmm0 0000000000000026 ret The "jne/jp/jmp" sequence can be reduced to this instead: _floatingPointComparison: 0000000000000000 cvtss2sd %xmm1,%xmm1 0000000000000004 cvtss2sd %xmm0,%xmm0 0000000000000008 mulsd %xmm1,%xmm0 000000000000000c pxor %xmm1,%xmm1 0000000000000010 ucomisd %xmm1,%xmm0 0000000000000014 jp 0x00000002 0000000000000016 je 0x00000008 0000000000000018 addsd 0x00000006(%rip),%xmm0 0000000000000020 cvtsd2ss %xmm0,%xmm0 0000000000000024 ret for a savings of 2 bytes. This xform can happen when we recognize that jne and jp jump to the same "true" MBB, the unconditional jump would jump to the "false" MBB, and the "true" branch is the fall-through MBB. llvm-svn: 97766
* Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit versionJohnny Chen2010-03-041-1/+27
| | | | | | of either sxtb16 or uxtb16, and the unified syntax does not specify ".w". llvm-svn: 97760
* pr6478: The frame pointer spill frame index is only defined when there is aBob Wilson2010-03-041-1/+3
| | | | | | frame pointer. llvm-svn: 97755
* pr6480: Don't try producing ld/st-multiple instructions when the address isBob Wilson2010-03-041-0/+5
| | | | | | | | an undef value. This is only going to come up for bugpoint-reduced tests -- correct programs will not access memory at undefined addresses -- so it's not worth the effort of doing anything more aggressive. llvm-svn: 97745
* Fix the remaining MUL8 and DIV8 to define AX instead of AL,AH.Jakob Stoklund Olesen2010-03-041-8/+11
| | | | | | | | | These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG reads AX in order to avoid reading AH with a REX instruction. Fix PR6489. llvm-svn: 97742
* Fix recognition of 16-bit bswap for C front-ends which emit theDan Gohman2010-03-041-3/+12
| | | | | | clobber registers in a different order. llvm-svn: 97741
* not committing what you test = bad.Chris Lattner2010-03-041-1/+2
| | | | llvm-svn: 97740
* make gep matching in fastisel match the base of the gep as aChris Lattner2010-03-041-1/+8
| | | | | | | register if it isn't possible to match the indexes *and* the base. This fixes some fast isel rejects of load instructions on oggenc. llvm-svn: 97739
* Added 32-bit Thumb instructions for Preload Data (PLD, PLDW) and PreloadJohnny Chen2010-03-041-1/+71
| | | | | | | | | | Instruction (PLI) for disassembly only. According to A8.6.120 PLI (immediate, literal), for example, different instructions are generated for "pli [pc, #0]" and "pli [pc, #-0"]. The disassembler solves it by mapping -0 (negative zero) to -1, -1 to -2, ..., etc. llvm-svn: 97731
* add a comment.Chris Lattner2010-03-041-0/+1
| | | | llvm-svn: 97709
* Teach the pic16 target to recognize pic16-*-* triples.John McCall2010-03-041-1/+2
| | | | llvm-svn: 97691
* Modified the asm string of 16-bit Thumb MUL instruction so that it prints:Johnny Chen2010-03-031-1/+1
| | | | | | | | MULS <Rdm>, <Rn>, <Rdm> according to A8.6.105 MUL Encoding T1. llvm-svn: 97675
* Fix PR6444, note still doesn't compile libgcc2 all the way, but fixes that ↵Andrew Lenharth2010-03-031-1/+2
| | | | | | error. May not fix it in an ABI complient way. It wasn't clear what gcc does llvm-svn: 97660
* Added 32-bit Thumb instructions LDRT, LDRBT, LDRHT,,LDRSBT, LDRSHT, STRT, STRBT,Johnny Chen2010-03-031-0/+41
| | | | | | and STRHT for disassembly only. llvm-svn: 97655
* remove nvload and two patterns that use it which are Chris Lattner2010-03-031-23/+0
| | | | | | better done by dag combine. llvm-svn: 97633
* Added 32-bit Thumb instructions t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV, and t2DBGJohnny Chen2010-03-031-0/+28
| | | | | | for disassembly only. llvm-svn: 97632
* factor the 'in the default address space' check out to a singleChris Lattner2010-03-031-51/+30
| | | | | | | 'dsload' pattern. tblgen doesn't check patterns to see if they're textually identical. This allows better factoring. llvm-svn: 97630
* factor the 'sign extended from 8 bit' patterns better so Chris Lattner2010-03-033-20/+11
| | | | | | | | that they are not destination type specific. This allows tblgen to factor them and the type check is redundant with what the isel does anyway. llvm-svn: 97629
* - Change MachineInstr::isIdenticalTo to take a new option that determines ↵Evan Cheng2010-03-032-6/+5
| | | | | | | | whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality. - Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools). llvm-svn: 97628
* Eliminate unused instruction classes.Evan Cheng2010-03-031-13/+0
| | | | llvm-svn: 97617
* Added 32-bit Thumb instructions t2DMB variants, t2DSB variants, and t2ISBsy forJohnny Chen2010-03-031-0/+60
| | | | | | disassembly only. llvm-svn: 97614
* merge two loops over all nodes in the graph into one.Chris Lattner2010-03-021-57/+41
| | | | llvm-svn: 97606
* eliminate PreprocessForRMW now that isel handles it.Chris Lattner2010-03-021-136/+27
| | | | | | We still preprocess calls and fp return stuff. llvm-svn: 97598
* remove 300 lines of code that is now dead in the MSP430 backendChris Lattner2010-03-021-293/+1
| | | | | | | now that isel handles chains more aggressively. This also allows us to make isLegalToFold non-virtual. llvm-svn: 97597
* Fix some issues in WalkChainUsers dealing with Chris Lattner2010-03-022-45/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | CopyToReg/CopyFromReg/INLINEASM. These are annoying because they have the same opcode before an after isel. Fix this by setting their NodeID to -1 to indicate that they are selected, just like what automatically happens when selecting things that end up being machine nodes. With that done, give IsLegalToFold a new flag that causes it to ignore chains. This lets the HandleMergeInputChains routine be the one place that validates chains after a match is successful, enabling the new hotness in chain processing. This smarter chain processing eliminates the need for "PreprocessRMW" in the X86 and MSP430 backends and enables MSP to start matching it's multiple mem operand instructions more aggressively. I currently #if out the dead code in the X86 backend and MSP backend, I'll remove it for real in a follow-on patch. The testcase changes are: test/CodeGen/X86/sse3.ll: we generate better code test/CodeGen/X86/store_op_load_fold2.ll: PreprocessRMW was miscompiling this before, we now generate correct code Convert it to filecheck while I'm at it. test/CodeGen/MSP430/Inst16mm.ll: Add a testcase for mem/mem folding to make anton happy. :) llvm-svn: 97596
* Added 32-bit Thumb instruction CLREX (Clear-Exclusive) for disassembly only.Johnny Chen2010-03-021-0/+10
| | | | llvm-svn: 97595
* Removed the extra S from the multiclass def T2I_adde_sube_s_irs as well as fromJohnny Chen2010-03-021-14/+14
| | | | | | | the opc string passed in, since it's a given from the class inheritance of T2sI. The fixed the extra 's' in adcss & sbcss when disassembly printing. llvm-svn: 97582
* Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,Johnny Chen2010-03-022-7/+164
| | | | | | | SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for disassembly only. llvm-svn: 97573
* AL is an optional mnemonic extension for always, except in IT instructions.Johnny Chen2010-03-024-1/+15
| | | | | | | Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing. Ref: A8.3 Conditional execution llvm-svn: 97571
* Change some asm shift opcode strings to lowercase.Johnny Chen2010-03-021-6/+6
| | | | llvm-svn: 97567
* fix typo add missing (Xerxes Ranby2010-03-021-2/+2
| | | | llvm-svn: 97565
* Unbreak llvm-arm-linux buildbot and fix PR5309.Xerxes Ranby2010-03-021-2/+2
| | | | llvm-svn: 97564
* Sink InstructionSelect() out of each target into SDISel, and rename itChris Lattner2010-03-0214-332/+42
| | | | | | | | | | | | DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader. Sink some other stuff out of DAGISelHeader into SDISel. Eliminate the various 'Indent' stuff from various targets, which dates to when isel was recursive. 17 files changed, 114 insertions(+), 430 deletions(-) llvm-svn: 97555
* Only save vector registers if we've defined for the vector registers.Eric Christopher2010-03-021-2/+2
| | | | | | Fixes PR5309. llvm-svn: 97554
* Remove dead parameter passing.Bill Wendling2010-03-026-11/+7
| | | | llvm-svn: 97536
* Floating-point add, sub, and mul are now spelled fadd, fsub, and fmul,Dan Gohman2010-03-022-5/+5
| | | | | | respectively. llvm-svn: 97531
* remove a little hack I did for the old isel, not neededChris Lattner2010-03-011-16/+2
| | | | | | now that it is gone. llvm-svn: 97516
* Remove the optimize for code size limitation on r67917. Optimize 64-bit imul ↵Evan Cheng2010-03-011-4/+0
| | | | | | by constants into leas + shl regardless if optimizing for code size. The size saving from using imulq isn't worth it. Also, the lea and shl instructions may expose further optimization. llvm-svn: 97507
* remove a terrible hack that disabled assertions from this file because of ↵Chris Lattner2010-03-011-9/+0
| | | | | | | | build time problems. rdar://7697850. llvm-svn: 97500
* stop using generated sdnodexforms.Chris Lattner2010-03-011-1/+5
| | | | llvm-svn: 97485
* Added STRHT for disassembly only and fixed a bug in AI3sthpo class where the WJohnny Chen2010-03-012-2/+10
| | | | | | bit should be set to 0 instead of 1. llvm-svn: 97481
* Add explicit keywords.Dan Gohman2010-03-012-2/+3
| | | | llvm-svn: 97460
* This is now done.Dan Gohman2010-03-011-5/+0
| | | | llvm-svn: 97450
* Add JIT support to the TODO list (test commit)Nathan Keynes2010-03-011-0/+1
| | | | llvm-svn: 97443
* 80-col violations/trailing whitespace.Mikhail Glushenkov2010-02-281-11/+12
| | | | llvm-svn: 97427
* remove redundant instruction.Chris Lattner2010-02-281-2/+2
| | | | llvm-svn: 97374
* Add a flag to addPassesToEmit* to disable the Verifier pass runDan Gohman2010-02-285-6/+12
| | | | | | after LSR, so that clients can opt in. llvm-svn: 97357
* Implement XMM subregs.Dan Gohman2010-02-285-163/+168
| | | | | | | | | | | Extracting the low element of a vector is now done with EXTRACT_SUBREG, and the zero-extension performed by load movss is now modeled with SUBREG_TO_REG, and so on. Register-to-register movss and movsd are no longer considered copies; they are two-address instructions which insert a scalar into a vector. llvm-svn: 97354
* The mayHaveSideEffects flag is no longer used.Dan Gohman2010-02-2712-26/+24
| | | | llvm-svn: 97348
* remove a bogus pattern, which had the same pattern as STDUChris Lattner2010-02-272-8/+1
| | | | | | | | | but codegen'd differently. This really wanted to use some sort of subreg to get the low 4 bytes of the G8RC register or something. However, it's invalid and nothing is testing it, so I'm just zapping the bogosity. llvm-svn: 97345
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