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* Expand ADDO/SUBO on HexagonKrzysztof Parzyszek2015-04-131-0/+8
| | | | llvm-svn: 234795
* Revert revisions r234755, r234759, r234760Jan Vesely2015-04-137-61/+2
| | | | | | | | | | | Revert "Remove default in fully-covered switch (to fix Clang -Werror -Wcovered-switch-default)" Revert "R600: Add carry and borrow instructions. Use them to implement UADDO/USUBO" Revert "LegalizeDAG: Try to use Overflow operations when expanding ADD/SUB" Using overflow operations fails CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll on hexagon, nvptx, and r600. Revert while I investigate. llvm-svn: 234768
* Allow memory intrinsics to be tail callsKrzysztof Parzyszek2015-04-1310-11/+20
| | | | llvm-svn: 234764
* R600: Add carry and borrow instructions. Use them to implement UADDO/USUBOJan Vesely2015-04-137-2/+61
| | | | | | | | | | | | | | | | v2: tighten the sub64 tests v3: rename to CARRY/BORROW v4: fixup test cmdline add known bits computation use sign extend instead of sub 0,x better add test v5: remove redundant break move lowering to separate functions fix comments Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewers: arsenm llvm-svn: 234759
* R600: Make FMIN/MAXNUM legal on all asicsJan Vesely2015-04-123-2/+7
| | | | | | | | v2: Add tests Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> reviewer: arsenm llvm-svn: 234716
* R600: remove manual BFE optimizationJan Vesely2015-04-121-8/+2
| | | | | | | | Fixed since r233079 Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> reviewer: arsenm llvm-svn: 234715
* [PowerPC] Really iterate over all loops in PPCLoopDataPrefetch/PPCLoopPreIncPrepHal Finkel2015-04-122-14/+6
| | | | | | | | When I fixed these a couple of days ago to iterate over all loops, not just depth == 1 loops, I inadvertently made it such that we'd only look at the first top-level loop. Make sure that we really look at all of them. llvm-svn: 234705
* [PowerPC] Disable part-word atomics on the P7Hal Finkel2015-04-111-2/+2
| | | | | | | As it turns out, even though these are part of ISA 2.06, the P7 does not support them (or, at least, not any P7s we're tested so far). llvm-svn: 234686
* Add direct moves to/from VSR and exploit them for FP/INT conversionsNemanja Ivanovic2015-04-118-1/+134
| | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D8928 It adds direct move instructions to/from VSX registers to GPR's. These are exploited for FP <-> INT conversions. llvm-svn: 234682
* Use 'override/final' instead of 'virtual' for overridden methodsAlexander Kornienko2015-04-1127-29/+31
| | | | | | | | | | | | | | The patch is generated using clang-tidy misc-use-override check. This command was used: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py \ -checks='-*,misc-use-override' -header-filter='llvm|clang' \ -j=32 -fix -format http://reviews.llvm.org/D8925 llvm-svn: 234679
* [PowerPC] Fix PPCLoopPreIncPrep for depth > 1 loopsHal Finkel2015-04-111-10/+27
| | | | | | | | | This pass had the same problem as the data-prefetching pass: it was only checking for depth == 1 loops in practice. Fix that, add some debugging statements, and make sure that, when we grab an AddRec, it is for the loop we expect. llvm-svn: 234670
* [CodeGen] Split -enable-global-merge into ARM and AArch64 options.Ahmed Bougacha2015-04-112-2/+16
| | | | | | | | | | | | | Currently, there's a single flag, checked by the pass itself. It can't force-enable the pass (and is on by default), because it might not even have been created, as that's the targets decision. Instead, have separate explicit flags, so that the decision is consistently made in the target. Keep the flag as a last-resort "force-disable GlobalMerge" for now, for backwards compatibility. llvm-svn: 234666
* [AArch64] Strengthen the code for the prologue insertion.Quentin Colombet2015-04-101-0/+2
| | | | | | | | | The spilled registers are pristine and thus, correctly handled by the register scavenger and so on, but the liveness information is strictly speaking wrong at this point. Fix that. llvm-svn: 234664
* [PowerPC] Prefetching should also consider depth > 1 loopsHal Finkel2015-04-101-2/+5
| | | | | | | Iterating over loops from the LoopInfo instance only provides top-level loops. We need to search the whole tree of loops to find the inner ones. llvm-svn: 234603
* [mips] [IAS] Improve comments in MipsAsmParser::expandLoadImm. NFC.Toma Tabacu2015-04-101-7/+5
| | | | llvm-svn: 234595
* [AArch64] Changes some SchedAlias to WriteRes for Cortex-A57.Chad Rosier2015-04-101-3/+8
| | | | | | | | | | | | Using SchedAliases is convenient and works well for latency and resource lookup for instructions. However, this creates an entry in AArch64WriteLatencyTable with a WriteResourceID of 0, breaking any SchedReadAdvance since the lookup will fail. http://reviews.llvm.org/D8043 Patch by Dave Estes <cestes@codeaurora.org>! llvm-svn: 234594
* [AArch64] Adjusts Cortex-A57 machine model to handle zero shift.Chad Rosier2015-04-101-0/+9
| | | | | | | http://reviews.llvm.org/D8043 Patch by Dave Estes <cestes@codeaurora.org>! llvm-svn: 234593
* Reduce dyn_cast<> to isa<> or cast<> where possible.Benjamin Kramer2015-04-1013-39/+36
| | | | | | No functional change intended. llvm-svn: 234586
* Divergence analysis for GPU programsJingyue Wu2015-04-102-0/+72
| | | | | | | | | | | | | | | | | | | Summary: Some optimizations such as jump threading and loop unswitching can negatively affect performance when applied to divergent branches. The divergence analysis added in this patch conservatively estimates which branches in a GPU program can diverge. This information can then help LLVM to run certain optimizations selectively. Test Plan: test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll Reviewers: resistor, hfinkel, eliben, meheff, jholewinski Subscribers: broune, bjarke.roune, madhur13490, tstellarAMD, dberlin, echristo, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8576 llvm-svn: 234567
* [PowerPC] Don't crash on PPC32 i64 fp_to_uint on modern coresHal Finkel2015-04-101-0/+1
| | | | | | | | | | When we have an instruction for this (and, thus, don't generate a runtime call), we need to custom type legalize this (in a trivial way, just as we do for fp_to_sint). Fixes PR23173. llvm-svn: 234561
* [AArch64] Promote f16 operations to f32.Ahmed Bougacha2015-04-101-8/+50
| | | | | | | | | | | | | | | | | | | | For the most common ones (such as fadd), we already did the promotion. Do the same thing for all the others. Currently, we'll just crash/assert on all these operations, as there's no hardware or libcall support whatsoever. f16 (half) is specified as an interchange - not arithmetic - format, and is expected to be promoted to single-precision for arithmetic operations. While there, teach the legalizer about promoting some of the (mostly floating-point) operations that we never needed before. Differential Revision: http://reviews.llvm.org/D8648 See related discussion on the thread for: http://reviews.llvm.org/D8755 llvm-svn: 234550
* Add LLVM support for remaining integer divide and permute instructions from ↵Nemanja Ivanovic2015-04-096-52/+133
| | | | | | | | | | | ISA 2.06 This is the patch corresponding to review: http://reviews.llvm.org/D8406 It adds some missing instructions from ISA 2.06 to the PPC back end. llvm-svn: 234546
* Simplify use of formatted_raw_ostream.Rafael Espindola2015-04-093-12/+14
| | | | | | | | | | | | | | | formatted_raw_ostream is a wrapper over another stream to add column and line number tracking. It is used only for asm printing. This patch moves the its creation down to where we know we are printing assembly. This has the following advantages: * Simpler lifetime management: std::unique_ptr * We don't compute column and line number of object files :-) llvm-svn: 234535
* [AArch64][FastISel] Fix integer extend optimization.Juergen Ributzka2015-04-091-5/+6
| | | | | | | | | | | | | | The integer extend optimization tries to fold the extend into the load instruction. This requires us to identify if the extend has already been emitted or not and act accordingly on it. The check that was originally performed for this was not sufficient. Besides checking the ValueMap for a mapped register we also need to check if the virtual register has already an associated machine instruction that defines it. This fixes rdar://problem/20470788. llvm-svn: 234529
* Remove duplicated code and consolidate initializers.Eric Christopher2015-04-092-15/+5
| | | | llvm-svn: 234525
* clang-format bits of code to make a followup patch easy to read.Rafael Espindola2015-04-0911-26/+16
| | | | llvm-svn: 234519
* Use a raw_svector_ostream instead of a raw_string_ostream.Rafael Espindola2015-04-091-6/+8
| | | | | | It saves a bit of copying. llvm-svn: 234507
* Don't repeat name in comment. NFC.Rafael Espindola2015-04-094-24/+22
| | | | llvm-svn: 234506
* This reverts commit r234460 and r234461.Rafael Espindola2015-04-093-8/+6
| | | | | | | | | Revert "Add classof implementations to the raw_ostream classes." Revert "Use the cast machinery to remove dummy uses of formatted_raw_ostream." The underlying issue can be fixed without classof. llvm-svn: 234495
* [ARM] support for Cortex-R4/R4FJaved Absar2015-04-092-1/+19
| | | | | | | | | Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
* [mips] Refactor saved-registers bitmask creation in ↵Toma Tabacu2015-04-091-20/+11
| | | | | | | | | | | | | | | | | | | MipsAsmPrinter::printSavedRegsBitmask. NFC. Summary: Make the code more readable by fusing the for-loops together and explicitly checking for each register class. Also, this version is more straightforward because it doesn't assume that FPU registers always come before CPU registers in the CalleeSavedInfo vector. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8033 llvm-svn: 234475
* [AArch64] Add support for dynamic stack alignmentKristof Beyls2015-04-094-43/+172
| | | | | | Differential Revision: http://reviews.llvm.org/D8876 llvm-svn: 234471
* [AArch64] Remove redundant -march option. Also fix a think-o from r234462.Lang Hames2015-04-091-1/+1
| | | | llvm-svn: 234467
* [AArch64] Teach AArch64TargetLowering::getOptimalMemOpType to consider alignmentLang Hames2015-04-091-1/+11
| | | | | | | | | | | | | restrictions when choosing a type for small-memcpy inlining in SelectionDAGBuilder. This ensures that the loads and stores output for the memcpy won't be further expanded during legalization, which would cause the total number of instructions for the memcpy to exceed (often significantly) the inlining thresholds. <rdar://problem/17829180> llvm-svn: 234462
* Use the cast machinery to remove dummy uses of formatted_raw_ostream.Rafael Espindola2015-04-093-6/+8
| | | | | | | If we know we are producing an object, we don't need to wrap the stream in a formatted_raw_ostream anymore. llvm-svn: 234461
* [ARM] make vminnm/vmaxnm work with ?le, ?ge and no-nans-fp-mathScott Douglass2015-04-081-9/+18
| | | | | | | | | | Because -menable-no-nans causes fcmp conditions to be rewritten without 'o' or 'u' the recognition code in needs to cope. Also extended it to handle 'le' and 'ge. Differential Revision: http://reviews.llvm.org/D8725 llvm-svn: 234421
* [mips] [IAS] Do not generate redundant move when expanding lw/sw with symbol.Toma Tabacu2015-04-081-6/+8
| | | | | | | | | | | | | | | | | | Summary: Even though there is no 2nd register operand in the "lw/sw $8, symbol" case, we still try to find one, and we end up with $0, which makes us generate an unnecessary "addu $8, $8, $0" (a.k.a. "move $8, $8"). We can avoid this by checking if the 2nd register operand is different from $0, before generating the addu. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8055 llvm-svn: 234406
* [mips] [IAS] Add support for the BNEZL and BEQZL pseudo-instructions.Toma Tabacu2015-04-081-0/+4
| | | | | | | | | | | | | | | | | Summary: They are of the form "bnezl/beqzl $rs, offset" and expand to "bnel/beql $rs, $zero, offset". These instructions are used in Linux inline assembly. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8540 llvm-svn: 234401
* [ARM][Debug Info] Restore emitting of .cfi_def_cfa_offset for functions ↵Sergey Dmitrouk2015-04-081-1/+2
| | | | | | | | | | | | | | | | without stack frame Summary: Looks like new code from [[ http://reviews.llvm.org/rL222057 | rL222057 ]] doesn't account for early `return` in `ARMFrameLowering::emitPrologue`, which leads to loosing `.cfi_def_cfa_offset` directive for functions without stack frame. Reviewers: echristo, rengolin, asl, t.p.northover Reviewed By: t.p.northover Subscribers: llvm-commits, rengolin, aemerson Differential Revision: http://reviews.llvm.org/D8606 llvm-svn: 234399
* [mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic.Toma Tabacu2015-04-081-4/+2
| | | | | | | | | | | | | | | | Summary: These AssemblerPredicate's are unnecessary and actually make some instructions unusable when assembling pre-MIPS32 ISAs. For example, this was causing the IAS to reject the 'j' instruction for MIPS I-V. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8300 llvm-svn: 234398
* [bpf] support BPF backend as shared libraryAlexei Starovoitov2015-04-081-1/+1
| | | | | | | | | dependencies were not set correctly for shared library build. static was ok Patch by Brenden Blanco. llvm-svn: 234386
* R600/SI: Add some missing overridesTom Stellard2015-04-082-2/+2
| | | | llvm-svn: 234384
* R600/SI: Initial support for assembler and inline assemblyTom Stellard2015-04-0814-133/+1369
| | | | | | | | | | | | | This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
* R600/SI: Add missing SOPK instructionsTom Stellard2015-04-083-13/+72
| | | | llvm-svn: 234380
* R600/SI: Don't print offset0/offset1 DS operands when they are 0Tom Stellard2015-04-081-4/+8
| | | | llvm-svn: 234379
* AArch64: disallow "fmov sD, #-0.0" during assembly.Tim Northover2015-04-071-3/+4
| | | | | | | | | | | | | We weren't checking the sign of the floating point immediate before translating it to "fmov sD, wzr". Similarly for D-regs. Technically "movi vD.2s, #0x80, lsl #24" would work most of the time, but it's not a blessed alias (and I don't think it should be since people expect writing sD to zero out the high lanes, and there's no dD equivalent). So an error it is. rdar://20455398 llvm-svn: 234372
* [ARM] Mark a bunch of .td Operands with type _MEMORY.Ahmed Bougacha2015-04-073-39/+42
| | | | | | | | | | | This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
* [bpf] fix buildAlexei Starovoitov2015-04-072-6/+3
| | | | | | | | fix the build and remove unused variable warnings in Release mode. Patch by Brenden Blanco. llvm-svn: 234349
* AArch64: Don't lower ISD::SELECT to ISD::SELECT_CCMatthias Braun2015-04-072-44/+60
| | | | | | | | | | | | | | | | Instead of lowering SELECT to SELECT_CC which is further lowered later immediately call the SELECT_CC lowering code. This is preferable because: - Avoids an unnecessary roundtrip through the legalization queues with an intermediate node. - More importantly: Lowered operations get visited last leading to SELECT_CC getting visited with legalized operands and unlegalized ones for preexisting SELECT_CC nodes. This does not hurt the current code (hence no testcase) but is required for another patch I am working on. Differential Revision: http://reviews.llvm.org/D8187 llvm-svn: 234334
* [mips] [IAS] Allow .set assignments for already defined symbols.Toma Tabacu2015-04-071-5/+1
| | | | | | | | | | | | | | | | Summary: This is not possible when using the IAS for MIPS, but it is possible when using the IAS for other architectures and when using GAS for MIPS. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8578 llvm-svn: 234316
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