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* Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually beJim Grosbach2010-10-062-7/+28
| | | | | | pseudo instructions. llvm-svn: 115840
* Add a 'pattern' arg to the ARM PseudoNeonI class.Jim Grosbach2010-10-062-7/+9
| | | | llvm-svn: 115831
* target operand flag values aren't a bitmaskJim Grosbach2010-10-061-2/+2
| | | | llvm-svn: 115798
* - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng2010-10-0610-41/+330
| | | | | | | | | | | | | allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
* enhance X86TypeInfo to include information about the encoding andChris Lattner2010-10-061-20/+36
| | | | | | | | operand kind for immediates. Use these to define a new BinOpRI class and switch AND8/16/32ri over to it. AND64ri32 needs some more refactoring before it can make the switcheroo. llvm-svn: 115752
* add a class for _REV nodes.Chris Lattner2010-10-061-19/+21
| | | | llvm-svn: 115748
* sink more intelligence into the ITy base class. Now it knowsChris Lattner2010-10-061-12/+21
| | | | | | | that i8 operations are even and i16,i32,i64 operations have a low opcode bit set (they are odd). llvm-svn: 115747
* refactor things a bit, now the REX_W and OpSize prefix bytes are inferred ↵Chris Lattner2010-10-061-22/+46
| | | | | | from the type info. llvm-svn: 115745
* with tblgen suitably extended, we can now get the load node from typeinfo.Chris Lattner2010-10-061-6/+6
| | | | llvm-svn: 115744
* lets go all meta and define new X86 type wrappers that declare the associatedChris Lattner2010-10-062-42/+65
| | | | | | | gunk that goes along with an MVT (e.g. reg class, preferred load operation, memory operand) llvm-svn: 115727
* introduce a new BinOpRM class and use it to factor AND*rm. This points outChris Lattner2010-10-061-21/+16
| | | | | | that I need a heavier handed approach to get ultimate factorization. llvm-svn: 115726
* remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 placesChris Lattner2010-10-061-8/+8
| | | | | | where !cast is just as short. llvm-svn: 115722
* replace stuff like:Chris Lattner2010-10-061-15/+11
| | | | | | | | | | | | | | let AsmString = !strconcat( !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)), !strconcat("\t", asm)); with: let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); :) llvm-svn: 115720
* allow !strconcat to take more than two operands to eliminateChris Lattner2010-10-053-16/+12
| | | | | | | | !strconcat(!strconcat(!strconcat(!strconcat Simplify some x86 td files to use it. llvm-svn: 115719
* Comment out fastisel debugging message.Eric Christopher2010-10-051-1/+1
| | | | llvm-svn: 115717
* associate the instruction suffix letter with the integer gpr Chris Lattner2010-10-052-18/+29
| | | | | | register class, and use this to simplify use of BinOpRR. llvm-svn: 115716
* introduce a new BinOpRR class, and convert 4 and instructions to use it.Chris Lattner2010-10-051-19/+12
| | | | llvm-svn: 115715
* Random cleanup and make the intermediate register in fptosi aEric Christopher2010-10-051-5/+5
| | | | | | | | 32-bit fp reg, not 64-bit. Fixes SingleSource. llvm-svn: 115711
* Move cmov pseudo instructions to InstrCompiler,Chris Lattner2010-10-052-582/+77
| | | | | | | | | | | convert all the rest of the cmovs to the multiclass, with good results: X86InstrCMovSetCC.td | 598 +-------------------------------------------------- X86InstrCompiler.td | 61 +++++ 2 files changed, 77 insertions(+), 582 deletions(-) llvm-svn: 115707
* Use #NAME# to have the CMOV multiclass define things with the same names as ↵Chris Lattner2010-10-054-43/+46
| | | | | | | | before (e.g. CMOVBE16rr instead of CMOVBErr16). llvm-svn: 115705
* enhance tblgen to support anonymous defm's, use this toChris Lattner2010-10-051-16/+16
| | | | | | simplify the X86 CMOVmr's. llvm-svn: 115702
* convert cmov mr patterns to use a multipattern. Death to redundancyChris Lattner2010-10-051-97/+25
| | | | | | and verbosity llvm-svn: 115701
* switch CMOVBE to the multipattern:Chris Lattner2010-10-054-53/+21
| | | | | | | | 21 insertions(+), 53 deletions(-) Moar change coming before I switch the rest. llvm-svn: 115697
* fix a bug I introduced in r115669, which ended up with MOV64mr_TCChris Lattner2010-10-051-1/+2
| | | | | | not getting marked as mayStore. This fixes llvm-gcc bootstrap. llvm-svn: 115693
* add a multiclass for cmov's, but don't start using it yet.Chris Lattner2010-10-051-1/+40
| | | | llvm-svn: 115692
* use a multipattern to define setcc instructions:Chris Lattner2010-10-051-173/+27
| | | | | | | X86InstrCMovSetCC.td | 200 ++++++--------------------------------------------- 1 file changed, 27 insertions(+), 173 deletions(-) llvm-svn: 115689
* move SETB pseudos into the same place in InstrCompiler.tdChris Lattner2010-10-052-21/+13
| | | | llvm-svn: 115686
* Replace a gross hack (the MOV64ri_alt instruction) with a slightly less Chris Lattner2010-10-053-11/+10
| | | | | | gross hack (having the asmmatcher handle the alias). llvm-svn: 115685
* distribute the rest of the contents of X86Instr64bit.td out toChris Lattner2010-10-054-331/+264
| | | | | | the right places. X86Instr64bit.td now dies, long live x86-64! llvm-svn: 115669
* move the rest of the simple 64-bit arithmetic into InstrArithmetic.tdChris Lattner2010-10-052-226/+195
| | | | llvm-svn: 115663
* continue moving 64-bit stuff into X86InstrArithmetic.tdChris Lattner2010-10-052-300/+245
| | | | llvm-svn: 115660
* Increase the number of bits used internally by the ARM target to represent theJim Grosbach2010-10-052-16/+16
| | | | | | addressing mode from four to five. llvm-svn: 115645
* move 64-bit add and adc to InstrArithmetic.Chris Lattner2010-10-052-113/+83
| | | | llvm-svn: 115632
* rewrote two addr constraints so that they are only set, not set and then ↵Chris Lattner2010-10-051-321/+343
| | | | | | nestedly cleared. llvm-svn: 115631
* split the 32-bit integer arithmetic instructions out to their own file.Chris Lattner2010-10-052-1226/+1246
| | | | llvm-svn: 115627
* integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight.Chris Lattner2010-10-052-302/+249
| | | | llvm-svn: 115608
* move 32-bit shift and rotates out to their own file.Chris Lattner2010-10-052-555/+579
| | | | llvm-svn: 115607
* add new fileChris Lattner2010-10-051-0/+162
| | | | llvm-svn: 115606
* move sign and zero extensions out to their own file.Chris Lattner2010-10-052-158/+7
| | | | llvm-svn: 115605
* move some instructions from Instr64Bit -> InstrInfo.Chris Lattner2010-10-053-98/+87
| | | | | | bswap32 doesn't read eflags. llvm-svn: 115604
* move CMOV_FR32 and friends to InstrCompiler, since they are Chris Lattner2010-10-054-57/+63
| | | | | | | | pseudo instructions. Move POPCNT to InstrSSE since they are SSE4 instructions. llvm-svn: 115603
* move various pattern matching support goop out of X86Instr64Bit, to liveChris Lattner2010-10-053-87/+70
| | | | | | with the 32-bit stuff. llvm-svn: 115602
* split conditional moves and setcc's out to their own file.Chris Lattner2010-10-054-814/+838
| | | | llvm-svn: 115601
* move string pseudo instructions to InstrCompiler consolidate 64-bit and ↵Chris Lattner2010-10-053-35/+36
| | | | | | 32-bit together. llvm-svn: 115600
* move the atomic pseudo instructions out to X86InstrCompiler.tdChris Lattner2010-10-054-393/+388
| | | | llvm-svn: 115599
* move more pseudo instructions out to X86InstrCompiler.tdChris Lattner2010-10-053-156/+153
| | | | llvm-svn: 115598
* move VMX instructions out to their own file.Chris Lattner2010-10-052-40/+56
| | | | llvm-svn: 115597
* continue moving stuff out to X86InstrSystem.td. MoveChris Lattner2010-10-055-1363/+1369
| | | | | | | | control flow stuff out to X86InstrControl.td. Move some compiler pseudo instructions and Pat<> patterns out to X86InstrCompiler.td llvm-svn: 115596
* fix MSVC 2010 build.Michael J. Spencer2010-10-051-1/+2
| | | | llvm-svn: 115594
* Cleanup Whitespace.Michael J. Spencer2010-10-051-11/+11
| | | | llvm-svn: 115593
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