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* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-216-31/+38
| | | | llvm-svn: 142682
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-216-22/+37
| | | | llvm-svn: 142675
* ARM VLD parsing and encoding.Jim Grosbach2011-10-216-247/+276
| | | | | | | | | | | | Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. llvm-svn: 142670
* Don't automatically set the "fc" bits on MSR instructions if the user didn't ↵Owen Anderson2011-10-211-3/+7
| | | | | | ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing. llvm-svn: 142669
* Nuke an #if0 that got accidentally left in.Jim Grosbach2011-10-211-31/+0
| | | | llvm-svn: 142658
* whitespace.Jim Grosbach2011-10-211-1/+1
| | | | llvm-svn: 142657
* Remove some outdated comments.Jim Grosbach2011-10-211-11/+11
| | | | llvm-svn: 142653
* Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with ↵Craig Topper2011-10-213-11/+71
| | | | | | custom isel lowering code. llvm-svn: 142642
* Fix unused variable warning.Richard Smith2011-10-211-1/+1
| | | | llvm-svn: 142630
* Revert r142618, r142622, and r142624, which were based on an incorrect ↵Owen Anderson2011-10-201-42/+4
| | | | | | reading of the ARMv7 docs. llvm-svn: 142626
* Disable the PPC hazard recognizer. It currently only supportsDan Gohman2011-10-201-2/+8
| | | | | | top-down scheduling and top-down scheduling is going away. llvm-svn: 142621
* Separate out ARM MSR instructions into M-class versions and AR-class ↵Owen Anderson2011-10-201-4/+42
| | | | | | versions. This fixes some roundtripping failures. llvm-svn: 142618
* Add missing operand. <rdar://problem/10313323>Bill Wendling2011-10-201-1/+2
| | | | llvm-svn: 142615
* Haven't yet found a nice way to handle TargetData verification in theLang Hames2011-10-201-25/+88
| | | | | | | | AsmParser. This patch adds validation for target data layout strings upon construction of TargetData objects. An attempt to construct a TargetData object from a malformed string will trigger an assertion. llvm-svn: 142605
* Tidy up. Trailing whitespace.Jim Grosbach2011-10-201-2/+2
| | | | llvm-svn: 142591
* ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.Jim Grosbach2011-10-201-4/+4
| | | | llvm-svn: 142583
* ARM VTBX (one register) assembly parsing and encoding.Jim Grosbach2011-10-201-3/+3
| | | | llvm-svn: 142581
* Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(Chad Rosier2011-10-203-32/+11
| | | | llvm-svn: 142557
* Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. ↵Evan Cheng2011-10-191-1/+2
| | | | | | rdar://10291355 llvm-svn: 142550
* Use literal pool loads instead of MOVW/MOVT for materializing global ↵James Molloy2011-10-191-3/+6
| | | | | | | | | | | | | | addresses when optimizing for size. On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is codesize including literal pools. The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries. Fixes PR11087. llvm-svn: 142530
* Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, ↵Bill Wendling2011-10-191-5/+27
| | | | | | use a constant pool. llvm-svn: 142485
* Remove some dead code.Bill Wendling2011-10-191-6/+0
| | | | llvm-svn: 142484
* Rename PEXTR to PEXT. Add intrinsics for BMI instructions.Craig Topper2011-10-191-24/+47
| | | | llvm-svn: 142480
* Emit the MOVT instruction only if the # LPads is > 64K.Bill Wendling2011-10-181-10/+20
| | | | llvm-svn: 142460
* For Thumb mode, we need to use a constant pool if the value is too large to beBill Wendling2011-10-181-3/+20
| | | | | | used with the CMP instruction. llvm-svn: 142458
* Revert "Turn on the vzeroupper pass by default."Eric Christopher2011-10-181-1/+1
| | | | | | This reverts commit 494f7ac3e8d2ab3d94e52317abf9c42a949fe1f3. llvm-svn: 142455
* ARM VTBL (one register) assembly parsing and encoding.Jim Grosbach2011-10-184-3/+101
| | | | llvm-svn: 142441
* Use the integer compare when the value is small enough. Use the "move into aBill Wendling2011-10-181-2/+17
| | | | | | | register and then compare against that" method when it's too large. We have to move the value into the register in the "movw, movt" pair of instructions. llvm-svn: 142440
* Turn on the vzeroupper pass by default.Eric Christopher2011-10-181-1/+1
| | | | | | I'll remove/rename the option in a few days. llvm-svn: 142439
* Use the integer compare when the value is small enough. Use the "move into aBill Wendling2011-10-181-6/+19
| | | | | | | register and then compare against that" method when it's too large. We have to move the value into the register in the "movw, movt" pair of instructions. llvm-svn: 142437
* Teach fast isel about vector stores, and make DoSelectCall return false when ↵Lang Hames2011-10-181-3/+24
| | | | | | it fails to emit a store. This fixes <rdar://problem/10215997>. llvm-svn: 142432
* The value we're comparing against may be too large for the ARM CMPBill Wendling2011-10-181-12/+16
| | | | | | | instruction. Move the value into a register and then use that for the CMP. <rdar://problem/10305266> llvm-svn: 142431
* The immediate may be too large for the CMP instruction. Move it into a registerBill Wendling2011-10-181-8/+13
| | | | | | | and use that in the CMP. <rdar://problem/10305266> llvm-svn: 142429
* Yet more ARM NEON assembly parsing for the lane index operand.Jim Grosbach2011-10-181-18/+18
| | | | llvm-svn: 142416
* ARM vmla/vmls assembly parsing for the lane index operand.Jim Grosbach2011-10-181-4/+4
| | | | llvm-svn: 142413
* ARM vmov assembly parsing for the lane index operand.Jim Grosbach2011-10-181-16/+16
| | | | llvm-svn: 142412
* Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.Andrew Trick2011-10-184-119/+112
| | | | | | | | Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
* Use isIntN and isUIntN to check for valid signed/unsigned numbers.Bob Wilson2011-10-181-3/+2
| | | | llvm-svn: 142395
* whitespaceAndrew Trick2011-10-182-7/+7
| | | | llvm-svn: 142394
* A landing pad could have more than one predecessor. In that case, we want thatBill Wendling2011-10-181-1/+8
| | | | | | | | | | predecessor to remove the jump to it as well. Delay clearing the 'landing pad' flag until after the jumps have been removed. (There is an implicit assumption in several modules that an MBB which jumps to a landing pad has only two successors.) <rdar://problem/10304224> llvm-svn: 142390
* ARM vmla/vmls assembly parsing for the lane index operand.Jim Grosbach2011-10-181-8/+8
| | | | llvm-svn: 142389
* ARM vqdmulh assembly parsing for the lane index operand.Jim Grosbach2011-10-181-4/+4
| | | | llvm-svn: 142386
* ARM vmul assembly parsing for the lane index operand.Jim Grosbach2011-10-181-4/+4
| | | | llvm-svn: 142381
* Final patch that completes old JIT support for Mips:Bruno Cardoso Lopes2011-10-187-91/+173
| | | | | | | | | | | | | | | | -Fix binary codes and rename operands in .td files so that automatically generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct encoding for instructions. -Define new class FMem for instructions that access memory. -Define new class FFRGPR for instructions that move data between GPR and FPU general and control registers. -Define custom encoder methods for memory operands, and also for size operands of ext and ins instructions. -Only static relocation model is currently implemented. Patch by Sasa Stankovic llvm-svn: 142378
* Fix incorrect check for sign-extended constant BUILD_VECTOR.Bob Wilson2011-10-181-1/+1
| | | | | | <rdar://problem/10298332> llvm-svn: 142371
* ARM vqdmlal assembly parsing for the lane index operand.Jim Grosbach2011-10-181-2/+2
| | | | llvm-svn: 142365
* Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it.Jim Grosbach2011-10-181-0/+2
| | | | llvm-svn: 142363
* ARM assembly parsing and encoding for VMOV.i64.Jim Grosbach2011-10-182-2/+32
| | | | llvm-svn: 142356
* PTX: Fix disabling of MAD instruction selectionJustin Holewinski2011-10-181-7/+14
| | | | llvm-svn: 142352
* Fix a bunch of unused variable warnings when doing a releaseDuncan Sands2011-10-183-8/+7
| | | | | | build with gcc-4.6. llvm-svn: 142350
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