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* [X86] Refactored LowerINTRINSIC_W_CHAIN to use a switch statament. NFCI.Simon Pilgrim2017-05-031-7/+9
| | | | | | Pre-commit as requested in D32769. llvm-svn: 302010
* [PowerPC, DAGCombiner] Fold a << (b % (sizeof(a) * 8)) back to a single ↵Tim Shen2017-05-031-0/+8
| | | | | | | | | | | | | | | | instruction Summary: This is the corresponding llvm change to D28037 to ensure no performance regression. Reviewers: bogner, kbarton, hfinkel, iteratee, echristo Subscribers: nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D28329 llvm-svn: 301990
* ARM: avoid handing a deleted node back to TableGen during ISel.Tim Northover2017-05-021-0/+4
| | | | | | | | | | When we replaced the multiplicand the destination node might already exist. When that happens the original gets CSEd and deleted. However, it's actually used as the offset so nonsense is produced. Should fix PR32726. llvm-svn: 301983
* Re-land r301697 "[IR] Make add/remove Attributes use AttrBuilder instead of ↵Reid Kleckner2017-05-021-5/+4
| | | | | | | | | | AttributeList" This time, I fixed, built, and tested clang. This reverts r301712. llvm-svn: 301981
* [AArch64] ILP32 Backend Relocation SupportJoel Jones2017-05-024-25/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove "_NC" suffix and semantics from TLSDESC_LD{64,32}_LO12 and TLSDESC_ADD_LO12 relocations Rearrange ordering in AArch64.def to follow relocation encoding Fix name: R_AARCH64_P32_LD64_GOT_LO12_NC => R_AARCH64_P32_LD32_GOT_LO12_NC Add support for several "TLS", "TLSGD", and "TLSLD" relocations for ILP32 Fix return values from isNonILP32reloc Add implementations for R_AARCH64_ADR_PREL_PG_HI21_NC, R_AARCH64_P32_LD32_GOT_LO12_NC, R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC, R_AARCH64_P32_TLSDESC_LD32_LO12, R_AARCH64_LD64_GOT_LO12_NC, *TLSLD_LDST128_DTPREL_LO12, *TLSLD_LDST128_DTPREL_LO12_NC, *TLSLE_LDST128_TPREL_LO12, *TLSLE_LDST128_TPREL_LO12_NC Modify error messages to give name of equivalent relocation in the ABI not being used, along with better checking for non-existent requested relocations. Added assembler support for "pg_hi21_nc" Relocation definitions added without implementations: R_AARCH64_P32_TLSDESC_ADR_PREL21, R_AARCH64_P32_TLSGD_ADR_PREL21, R_AARCH64_P32_TLSGD_ADD_LO12_NC, R_AARCH64_P32_TLSLD_ADR_PREL21, R_AARCH64_P32_TLSLD_ADR_PAGE21, R_AARCH64_P32_TLSLD_ADD_LO12_NC, R_AARCH64_P32_TLSLD_LD_PREL19, R_AARCH64_P32_TLSDESC_LD_PREL19, R_AARCH64_P32_TLSGD_ADR_PAGE21, R_AARCH64_P32_TLS_DTPREL, R_AARCH64_P32_TLS_DTPMOD, R_AARCH64_P32_TLS_TPREL, R_AARCH64_P32_TLSDESC Fix encoding: R_AARCH64_P32_TLSDESC_ADR_PAGE21 Reviewers: Peter Smith Patch by: Joel Jones (jjones@cavium.com) Differential Revision: https://reviews.llvm.org/D32072 llvm-svn: 301980
* ARM: add arm1176j-f processorTim Northover2017-05-021-0/+1
| | | | | | | | | I doubt anyone actually uses it, and I'm not even entirely convinced it exists myself; but it is our default for "clang -arch armv6". Functionally, if it does exist it's identical to the arm1176jz-f from LLVM's point of view (the difference is apparently in the "Security Extensions"). llvm-svn: 301962
* AMDGPU: Don't promote alloca to LDS for leaf functionsMatt Arsenault2017-05-021-1/+8
| | | | | | LDS use in leaf functions not currently handled. llvm-svn: 301958
* [Hexagon] Fix uninitialized value caught with valgrindKrzysztof Parzyszek2017-05-021-1/+1
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301957
* [Hexagon] Change iconst to emit 27bit relocationKrzysztof Parzyszek2017-05-0212-25/+32
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301956
* [Hexagon] Add extenders for GD_PLT_B22_PCREL and LD_PLT_B22_PCRELKrzysztof Parzyszek2017-05-026-5/+49
| | | | | | Patch by Sid Manning. llvm-svn: 301955
* [Hexagon] Don't ignore mult-cycle latency informationKrzysztof Parzyszek2017-05-023-15/+30
| | | | | | | | | | | | | | | | | | | | | | | | The compiler was generating code that ends up ignoring a multiple latency dependence between two instructions by scheduling the intructions in back-to-back packets. The packetizer needs to end a packet if the latency of the current current insruction and the source in the previous packet is greater than 1 cycle. This case occurs when there is still room in the current packet, but scheduling the instruction causes a stall. Instead, the packetizer should start a new packet. Also, if the current packet already contains a stall, then it is okay to add another instruction to the packet that also causes a stall. This occurs when there are no instructions that can be scheduled in between the producer and consumer instructions. This patch changes the latency for loads to 2 cycles from 3 cycles. This change refects that a load only needs to be separated by one extra packet to eliminate the stall. Patch by Ikhlas Ajbar. llvm-svn: 301954
* [Hexagon] Formatting changes, NFCKrzysztof Parzyszek2017-05-024-8/+13
| | | | llvm-svn: 301953
* [Hexagon] Remove unused validSubtarget TSFlagsKrzysztof Parzyszek2017-05-028-58/+4
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301952
* [Hexagon] Make sure duplexed dealloc_returns are checked for double jumpsKrzysztof Parzyszek2017-05-021-0/+8
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301951
* [Hexagon] Move checking AXOK to checkerKrzysztof Parzyszek2017-05-023-69/+80
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301949
* [Hexagon] Remove unneeded code from HexagonShufflerKrzysztof Parzyszek2017-05-022-11/+9
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301947
* [Hexagon] Extract function that checks endloops with other branchesKrzysztof Parzyszek2017-05-022-36/+39
| | | | | | | | Change location number to point to conflicting branch instruction. Patch by Colin LeMahieu. llvm-svn: 301946
* [Hexagon] Add new packet iterator which will iterate through duplexesKrzysztof Parzyszek2017-05-023-24/+82
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301945
* Revert "Remove "_NC" suffix and semantics from TLSDESC_LD{64,32}_LO12 and"Zachary Turner2017-05-024-110/+25
| | | | | | | | This reverts commit c08155afc5d3230792da2ad30a046a8617735a73. This is causing undefined symbol errors with some of the constants. llvm-svn: 301944
* [Hexagon] Check for .cur def without use without using a map data structureKrzysztof Parzyszek2017-05-022-24/+42
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301943
* Remove "_NC" suffix and semantics from TLSDESC_LD{64,32}_LO12 andJoel Jones2017-05-024-25/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TLSDESC_ADD_LO12 relocations Rearrange ordering in AArch64.def to follow relocation encoding Fix name: R_AARCH64_P32_LD64_GOT_LO12_NC => R_AARCH64_P32_LD32_GOT_LO12_NC Add support for several "TLS", "TLSGD", and "TLSLD" relocations for ILP32 Fix return values from isNonILP32reloc Add implementations for R_AARCH64_ADR_PREL_PG_HI21_NC, R_AARCH64_P32_LD32_GOT_LO12_NC, R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC, R_AARCH64_P32_TLSDESC_LD32_LO12, R_AARCH64_LD64_GOT_LO12_NC, *TLSLD_LDST128_DTPREL_LO12, *TLSLD_LDST128_DTPREL_LO12_NC, *TLSLE_LDST128_TPREL_LO12, *TLSLE_LDST128_TPREL_LO12_NC Modify error messages to give name of equivalent relocation in the ABI not being used, along with better checking for non-existent requested relocations. Added assembler support for "pg_hi21_nc" Relocation definitions added without implementations: R_AARCH64_P32_TLSDESC_ADR_PREL21, R_AARCH64_P32_TLSGD_ADR_PREL21, R_AARCH64_P32_TLSGD_ADD_LO12_NC, R_AARCH64_P32_TLSLD_ADR_PREL21, R_AARCH64_P32_TLSLD_ADR_PAGE21, R_AARCH64_P32_TLSLD_ADD_LO12_NC, R_AARCH64_P32_TLSLD_LD_PREL19, R_AARCH64_P32_TLSDESC_LD_PREL19, R_AARCH64_P32_TLSGD_ADR_PAGE21, R_AARCH64_P32_TLS_DTPREL, R_AARCH64_P32_TLS_DTPMOD, R_AARCH64_P32_TLS_TPREL, R_AARCH64_P32_TLSDESC Fix encoding: R_AARCH64_P32_TLSDESC_ADR_PAGE21 Reviewers: Peter Smith Patch by: Joel Jones (jjones@cavium.com) Differential Revision: https://reviews.llvm.org/D32072 llvm-svn: 301939
* AMDGPU: Refactor AsmPrinterMatt Arsenault2017-05-022-128/+245
| | | | | | | Avoid analyzing functions multiple times. This allows asserting that each function is only analyzed once. llvm-svn: 301938
* AMDGPU: Make intrinsics speculatableMatt Arsenault2017-05-021-1/+1
| | | | llvm-svn: 301937
* AMDGPU: Add AMDGPU_HS calling conventionMarek Olsak2017-05-027-0/+7
| | | | | | | | | | Reviewers: arsenm, nhaehnle Subscribers: mehdi_amini, kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D32644 llvm-svn: 301930
* [X86] Tidyup subvector insert/extract helpers. NFCI.Simon Pilgrim2017-05-021-24/+9
| | | | | | Use getConstantOperandVal where possible. llvm-svn: 301912
* Fix typo in comment. NFCI.Simon Pilgrim2017-05-021-2/+2
| | | | llvm-svn: 301911
* [ARM] GlobalISel: Use TableGen instruction selectorDiana Picus2017-05-025-22/+57
| | | | | | | | | | | Emit and use the TableGen instruction selector for ARM. At the moment, this allows us to remove the hand-written code for selecting G_SDIV and G_UDIV. Future commits will focus on increasing the code coverage for it and removing more dead code from the current instruction selector. llvm-svn: 301905
* [AVR] Save/restore the frame pointer for all functionsDylan McKay2017-05-021-11/+10
| | | | | | | A recent commit I made made it so that we only did this for signal or interrupt handlers. This broke normal functions. llvm-svn: 301893
* [PowerPC] Emit VMX loads/stores for aligned ops to avoid adding swaps on LENemanja Ivanovic2017-05-022-6/+23
| | | | | | | | | | | | | Fixes PR30730. This is a re-commit of a pulled commit. The commit was pulled because some software projects contained uses of Altivec vectors that violated alignment requirements. Known issues have now been fixed. Committing on behalf of Lei Huang. Differential Revision: https://reviews.llvm.org/D26861 llvm-svn: 301892
* [AVR] Fix a bug where the frame pointer is clobberedDylan McKay2017-05-021-7/+17
| | | | | | | | | | | | | | | Because it was a callee-saved register, we automatically generated code to spill and unspill its original value so that it is restored after the function returns. The problem is that this code was being generated before the epilogue. The epilogue itself uses the Y register, which could be prematurely restored by the CSR restoration process. This removes R29R28 from the CSR list and changes the prologue/epilogue code to handle it explicitly. llvm-svn: 301887
* [AVR] Enable the frame pointer for all functionsDylan McKay2017-05-011-2/+3
| | | | | | | This is a temporary measure while we figure out a way to get the frame pointer working correctly. llvm-svn: 301881
* [X86] Reduce code for setting operations actions by merging into loops ↵Simon Pilgrim2017-05-011-129/+68
| | | | | | across multiple types/ops. NFCI. llvm-svn: 301879
* [AArch64] Move GISel accessor initialization from TargetMachine to Subtarget.Quentin Colombet2017-05-012-56/+64
| | | | | | NFC llvm-svn: 301841
* [X86][AVX] Rename LowerVectorBroadcast to lowerBuildVectorAsBroadcast. NFCI.Simon Pilgrim2017-05-011-11/+8
| | | | | | Since the shuffle refactor, this is only used during BUILD_VECTOR lowering. llvm-svn: 301834
* [Hexagon] Replace CVI_VM_CUR_LD type with CVI_VM_LDKrzysztof Parzyszek2017-05-0110-114/+187
| | | | | | | | A .cur instruction can be identified by checking isCVINew() && mayLoad(). Patch by Colin LeMahieu. llvm-svn: 301829
* [Hexagon] Improving error reporting for writing to read only registersKrzysztof Parzyszek2017-05-013-8/+23
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301828
* [Hexagon] Give better error messages for solo instruction errorsKrzysztof Parzyszek2017-05-012-7/+11
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301827
* [Hexagon] Improve shuffle error reportingKrzysztof Parzyszek2017-05-0111-482/+276
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301823
* X86: initialize a few subtarget variables.Tim Northover2017-05-011-0/+3
| | | | | | Otherwise an indeterminate value gets read, causing a bunch of UBSan failures. llvm-svn: 301819
* Rename WeakVH to WeakTrackingVH; NFCSanjoy Das2017-05-012-14/+14
| | | | | | This relands r301424. llvm-svn: 301812
* [WebAssembly] Fix use of SDNodeFlags after API change in r301803Derek Schuff2017-05-011-2/+2
| | | | llvm-svn: 301811
* Remove unnecessary conditions as suggested by clang-tidy. NFCGabor Horvath2017-05-011-1/+1
| | | | | | | | Patch by: Gergely Angeli! Differential Revision: https://reviews.llvm.org/D31936 llvm-svn: 301807
* Generalize the specialized flag-carrying SDNodes by moving flags into SDNode.Amara Emerson2017-05-016-34/+32
| | | | | | | | This removes BinaryWithFlagsSDNode, and flags are now all passed by value. Differential Revision: https://reviews.llvm.org/D32527 llvm-svn: 301803
* [AVR] Implement non-constant bit rotationsDylan McKay2017-05-013-1/+63
| | | | | | This lets us do bit rotations of variable amount. llvm-svn: 301794
* [GlobalISel][X86] Prioritize Tablegen-erated instruction selection. NFCIgor Breger2017-05-011-50/+8
| | | | | | | | | | | | | | | | Summary: Prioritizes Tablegen-erated instruction selection over C++ instruction selection. Remove G_ADD/G_SUB C++ selection - implemented by Tablegen. Reviewers: dsanders, zvi, guyblank Reviewed By: guyblank Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32677 llvm-svn: 301792
* [GlobalISel][X86] G_SEXT/G_ZEXT support.Igor Breger2017-05-011-0/+20
| | | | | | | | | | | | Reviewers: zvi, guyblank Reviewed By: zvi Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32591 llvm-svn: 301790
* [GlobalISel][X86] G_LOAD/G_STORE pointer selection support.Igor Breger2017-05-011-2/+2
| | | | | | | | | | | | | | Summary: [GlobalISel][X86] G_LOAD/G_STORE pointer selection support. Reviewers: zvi, guyblank Reviewed By: zvi, guyblank Subscribers: dberris, rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D32217 llvm-svn: 301788
* [AVR] Fix a bug so that we now emit R_AVR_16 fixups with the correct offsetDylan McKay2017-04-303-8/+9
| | | | | | | Before this, the LDS/STS instructions would have their opcodes overwritten while linking. llvm-svn: 301782
* Do not legalize large add with addc/adde, introduce addcarry and do it with ↵Amaury Sechet2017-04-302-0/+65
| | | | | | | | | | | | | | uaddo/addcarry Summary: As per discution on how to get better codegen an large int legalization, it became clear that using a glue for the carry was preventing several desirable optimizations. Passing the carry down as a value allow for more flexibility. Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D29872 llvm-svn: 301775
* [APInt] Replace calls to setBits with more specific calls to setBitsFrom and ↵Craig Topper2017-04-301-3/+3
| | | | | | setLowBits where possible. llvm-svn: 301768
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