summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* [Hexagon] Disable predicated calls by defaultKrzysztof Parzyszek2017-05-053-1/+18
| | | | llvm-svn: 302307
* [Hexagon] Remove C6 and C7 as separate registersKrzysztof Parzyszek2017-05-053-20/+6
| | | | | | | These are M0 and M1. Removing duplicated registers reduces the number of explicit register aliasing. llvm-svn: 302306
* [RDF] Remove covered parts of reached uses for phi and use in same blockKrzysztof Parzyszek2017-05-053-13/+36
| | | | llvm-svn: 302305
* ARM: Compute MaxCallFrame size earlyMatthias Braun2017-05-053-4/+18
| | | | | | | | | | | | | | | | | This exposes a method in MachineFrameInfo that calculates MaxCallFrameSize and calls it after instruction selection in the ARM target. This avoids ARMBaseRegisterInfo::canRealignStack()/ARMFrameLowering::hasReservedCallFrame() giving different answers in early/late phases of codegen. The testcase shows a particular nasty example result of that where we would fail to properly align an alloca. Differential Revision: https://reviews.llvm.org/D32622 llvm-svn: 302303
* [AMDGPU] In the new waitcnt insertion pass, use getHeader Kannan Narayanan2017-05-051-5/+5
| | | | | | | | instead of getTopBlock to find the loop header. Differential Revision: https://reviews.llvm.org/D32831 llvm-svn: 302290
* [X86] Use SDValue::getConstantOperandVal helper. NFCI.Simon Pilgrim2017-05-051-9/+6
| | | | llvm-svn: 302286
* AMDGPU/AMDHSA: Set COMPUTE_PGM_RSRC2:LDS_SIZE to 0Konstantin Zhuravlyov2017-05-051-1/+2
| | | | | | | | This field is populated by the CP Differential Revision: https://reviews.llvm.org/D32619 llvm-svn: 302277
* [bpf] fix a bug which causes incorrect big endian reloc fixupAlexei Starovoitov2017-05-051-1/+1
| | | | | | | | o Add bpfeb support in BPF dwarfdump unit test case Signed-off-by: Yonghong Song <yhs@fb.com> Signed-off-by: Alexei Starovoitov <ast@fb.com> llvm-svn: 302265
* [KnownBits] Add wrapper methods for setting and clear all bits in the ↵Craig Topper2017-05-056-8/+9
| | | | | | | | | | underlying APInts in KnownBits. This adds routines for reseting KnownBits to unknown, making the value all zeros or all ones. It also adds methods for querying if the value is zero, all ones or unknown. Differential Revision: https://reviews.llvm.org/D32637 llvm-svn: 302262
* [AArch64] Remove AArch64AddressTypePromotion passJun Bum Lim2017-05-054-505/+0
| | | | | | | | | | | | | | | | Summary: Remove the AArch64AddressTypePromotion pass as we migrated all transformations done in this pass into CGP in r299379. Reviewers: qcolombet, jmolloy, javed.absar, mcrosier Reviewed By: qcolombet Subscribers: aemerson, rengolin, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D31623 llvm-svn: 302245
* [X86][AVX512] Improve support and testing for CTLZ of 512-bit vectors ↵Simon Pilgrim2017-05-051-3/+7
| | | | | | without CDI llvm-svn: 302233
* [X86] Remove duplicate operation actions. NFCI.Simon Pilgrim2017-05-051-5/+0
| | | | llvm-svn: 302230
* [X86][AVX512CDI] Move v2i64/v4i64 and v4i32/v8i32 VPLZCNT lowering to tablegenSimon Pilgrim2017-05-052-39/+38
| | | | | | Extend NoVLX targets to use the 512-bit versions llvm-svn: 302229
* Remove unused variableSimon Pilgrim2017-05-051-1/+0
| | | | llvm-svn: 302226
* [ARM] Add support for ORR and ORN instruction substitutionsJohn Brawn2017-05-051-0/+13
| | | | | | | | | | | | | Recently support was added for substituting one intruction for another by negating or inverting the immediate, but ORR and ORN were missed so this patch adds them. This one is slightly different to the others in that ORN only exists in thumb, so we only do the substitution in thumb. Differential Revision: https://reviews.llvm.org/D32534 llvm-svn: 302224
* [X86][AVX] Add LowerIntUnary helpers to split unary vector ops in half. NFCI.Simon Pilgrim2017-05-051-76/+51
| | | | | | Same as LowerIntArith helpers but for unary ops instead of binary. llvm-svn: 302222
* [X86] Remove unused code from X86 optimize LEAs. NFC.Andrew Ng2017-05-051-8/+0
| | | | | | | This patch removes unused code which is no longer required because of changes to the DIExpression::prepend function. llvm-svn: 302219
* Initialize new member X86Operand::FrontendSize in all codepaths.Daniel Jasper2017-05-051-1/+2
| | | | | | This fixes MSAN-builds after r302179. llvm-svn: 302214
* AMDGPU: GFX9 GS and HS shaders always have the scratch wave offset in SGPR5Marek Olsak2017-05-043-5/+20
| | | | | | | | | | Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D32645 llvm-svn: 302200
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-05-041-3/+3
| | | | llvm-svn: 302192
* [PPC] When restoring R30 (PIC base pointer), mark it as <def>Krzysztof Parzyszek2017-05-041-2/+1
| | | | | | | | | This happened on the PPC32/SVR4 path and was discovered when building FreeBSD on PPC32. It was a typo-class error in the frame lowering code. This fixes PR26519. llvm-svn: 302183
* [ms-inline-asm] Use the frontend size only for ambiguous instructionsReid Kleckner2017-05-042-66/+39
| | | | | | | | | | | | | | | | | | This avoids problems on code like this: char buf[16]; __asm { movups xmm0, [buf] mov [buf], eax } The frontend size in this case (1) is wrong, and the register makes the instruction matching unambiguous. There are also enough bytes available that we shouldn't complain to the user that they are potentially using an incorrectly sized instruction to access the variable. Supersedes D32636 and D26586 and fixes PR28266 llvm-svn: 302179
* [SystemZ] Make copyPhysReg() add impl-use operands of super reg.Jonas Paulsson2017-05-041-1/+7
| | | | | | | | | When a 128 bit COPY is lowered into two instructions, an impl-use operand of the super-reg should be added to each new instruction in case one of the sub-regs is undefined. Review: Ulrich Weigand llvm-svn: 302146
* [mips][XRay] Use the base version of emitXRayTableSimon Dardis2017-05-041-34/+1
| | | | | | | | | | | | | | Follow up rL290858 by removing the MIPS specific version of XRayTable emission in favour of the basic version. This resolves a buildbot failure where the ELF sections were malformed causing the linker to reject the object files with xray related sections. Reviewers: dberris, slthakur Differential Revision: https://reviews.llvm.org/D32808 llvm-svn: 302138
* [X86][AVX-512] Allow EVEX encoded instruction selection when available for ↵Igor Breger2017-05-041-2/+2
| | | | | | | | mul v8i32. Differential Revision: https://reviews.llvm.org/D32679 llvm-svn: 302127
* [ARM] ACLE Chapter 9 intrinsicsSam Parker2017-05-044-139/+338
| | | | | | | | | | | | Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
* [X86] Disabling PLT in Regcall CC FunctionsOren Ben Simhon2017-05-041-2/+8
| | | | | | | | | | According to psABI, PLT stub clobbers XMM8-XMM15. In Regcall calling convention those registers are used for passing parameters. Thus we need to prevent lazy binding in Regcall. Differential Revision: https://reviews.llvm.org/D32430 llvm-svn: 302124
* [AVX] Fix vpcmpeqq predicate.Igor Breger2017-05-041-2/+3
| | | | | | | | | | | | | | | | Summary: Fix vpcmpeqq predicate. AVX512 version of vpcmpeqq is not equivalent to AVX one. Split from https://reviews.llvm.org/D32679 Reviewers: craig.topper, zvi, aymanmus Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32786 llvm-svn: 302119
* Mark functions as not having CFI once we finalize an x86 stack frameReid Kleckner2017-05-031-0/+4
| | | | | | | | | We'll set it back to true in emitPrologue if it gets called. It doesn't get called for naked functions. Fixes PR32912 llvm-svn: 302092
* [KnownBits] Add zext, sext, and trunc methods to KnownBitsCraig Topper2017-05-031-2/+1
| | | | | | | | This patch adds zext, sext, and trunc methods to KnownBits and uses them where possible. Differential Revision: https://reviews.llvm.org/D32784 llvm-svn: 302088
* [AArch64] armv8-A doesn't have CRC.Ahmed Bougacha2017-05-031-1/+0
| | | | | | | | | | | That's only a required extension as of v8.1a. Remove it from the "generic" CPU as well: it should only support the base ISA (and binutils agrees). Also unify the MC tests into crc.s and arm64-crc32.s llvm-svn: 302077
* [Hexagon] Use automatically-generated scheduling information for HVXKrzysztof Parzyszek2017-05-0327-8023/+9998
| | | | | | Patch by Jyotsna Verma. llvm-svn: 302073
* [IR] Abstract away ArgNo+1 attribute indexing as much as possibleReid Kleckner2017-05-033-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Do three things to help with that: - Add AttributeList::FirstArgIndex, which is an enumerator currently set to 1. It allows us to change the indexing scheme with fewer changes. - Add addParamAttr/removeParamAttr. This just shortens addAttribute call sites that would otherwise need to spell out FirstArgIndex. - Remove some attribute-specific getters and setters from Function that take attribute list indices. Most of these were only used from BuildLibCalls, and doesNotAlias was only used to test or set if the return value is malloc-like. I'm happy to split the patch, but I think they are probably easier to review when taken together. This patch should be NFC, but it sets the stage to change the indexing scheme to this, which is more convenient when indexing into an array: 0: func attrs 1: retattrs 2...: arg attrs Reviewers: chandlerc, pete, javed.absar Subscribers: david2050, llvm-commits Differential Revision: https://reviews.llvm.org/D32811 llvm-svn: 302060
* [X86][LWP] Add stack folding mappings and tests for LWPINS/LWPVAL instructionsSimon Pilgrim2017-05-031-0/+6
| | | | llvm-svn: 302049
* Silence a 'enum and non-enum used in conditional' warning.Simon Pilgrim2017-05-031-1/+1
| | | | llvm-svn: 302048
* [X86][LWP] Add llvm support for LWP instructions (reapplied).Simon Pilgrim2017-05-037-0/+88
| | | | | | | | | | This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Reapplied - this time without changing line endings of existing files. Differential Revision: https://reviews.llvm.org/D32769 llvm-svn: 302041
* Revert rL302028 due to accidental line ending changes.Simon Pilgrim2017-05-037-750/+662
| | | | llvm-svn: 302038
* [Hexagon] Handle S2_storerf_io in HexagonInstrInfoKrzysztof Parzyszek2017-05-031-0/+1
| | | | llvm-svn: 302036
* [Hexagon] Misc fixes in HexagonInstrInfo, NFCKrzysztof Parzyszek2017-05-031-15/+2
| | | | | | Formatting changes + remove unused function. llvm-svn: 302035
* [Hexagon] Adjust latency between allocframe and the first store on stackKrzysztof Parzyszek2017-05-031-0/+5
| | | | | | | | | | | | Allocframe and the following stores on the stack have a latency of 2 cycles when not in the same packet. This happens because R29 is needed early by the store instruction. Since one of such stores can be packetized along with allocframe and use old value of R29, we can assign it 0 cycle latency while leaving latency of other stores to the default value of 2 cycles. Patch by Jyotsna Verma. llvm-svn: 302034
* [Hexagon] Handle J2_jumptpt and J2_jumpfpt in HexagonInstrInfoKrzysztof Parzyszek2017-05-031-8/+25
| | | | llvm-svn: 302033
* [Hexagon] Implement undoing .cur instructions in packetizerKrzysztof Parzyszek2017-05-033-2/+25
| | | | | | | | | | | | | The packetizer needs to convert .cur instruction to its regular form if the use is not in the same packet as the .cur. The code in the packetizer handles one type of .cur, which is the vector load case. This patch updates the packetizer so that it can undo all the .cur instructions. In the test case, the .cur is the 128B version, but there are also the post-increment versions. Patch by Brendon Cahoon. llvm-svn: 302032
* [Hexagon] Add memory operands to a rewritten loadKrzysztof Parzyszek2017-05-031-2/+3
| | | | llvm-svn: 302030
* [Hexagon] Reset spill alignment when variable-sized objects are presentKrzysztof Parzyszek2017-05-031-0/+30
| | | | llvm-svn: 302029
* [X86][LWP] Add llvm support for LWP instructions.Simon Pilgrim2017-05-037-662/+750
| | | | | | | | This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Differential Revision: https://reviews.llvm.org/D32769 llvm-svn: 302028
* [X86][AVX512] remove unnecessary case. NFCGuy Blank2017-05-031-2/+1
| | | | | | | | VFPCLASS is for vector types and not scalar, so it cannot get here. Differential Revision: https://reviews.llvm.org/D32694 llvm-svn: 302023
* [SystemZ] Properly check number of operands in getCmpOpsType()Jonas Paulsson2017-05-031-3/+4
| | | | | | | | It is needed to check that the number of operands are 2 when finding the case of a logic combination, e.g. 'and' of two compares. Review: Ulrich Weigand llvm-svn: 302022
* [X86] Support of no_caller_saved_registers attributeOren Ben Simhon2017-05-033-8/+40
| | | | | | | | | This patch implements the LLVM part for no_caller_saved_registers attribute as appears here: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=5ed3cc7b66af4758f7849ed6f65f4365be8223be. In order to implement the attribute, we use the dynamic CSR mechanism to remove returned/passed arguments from the function regmask/CSR list. Differential Revision: https://reviews.llvm.org/D31876 llvm-svn: 302020
* [AVR] Reserve the Y register in all functionsDylan McKay2017-05-031-6/+12
| | | | llvm-svn: 302017
* Revert "[AVR] Enable the frame pointer for all functions"Dylan McKay2017-05-031-3/+2
| | | | | | This reverts commit 358ad02d999e88853d2cfc954bd2f668308a51f7. llvm-svn: 302014
OpenPOWER on IntegriCloud