| Commit message (Collapse) | Author | Age | Files | Lines |
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1. Makes it possible to lower with floating point loads and stores.
2. Avoid unaligned loads / stores unless it's fast.
3. Fix some memcpy lowering logic bug related to when to optimize a
load from constant string into a constant.
4. Adjust x86 memcpy lowering threshold to make it more sane.
5. Fix x86 target hook so it uses vector and floating point memory
ops more effectively.
rdar://7774704
llvm-svn: 100090
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llvm-svn: 100089
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aes instead of sse4.2. Add a brief todo for a subtarget flag and rework
the aeskeygenassist instruction to more closely match the docs.
llvm-svn: 100078
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llvm-svn: 100066
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llvm-svn: 100042
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llvm-svn: 100037
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llvm-svn: 100033
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llvm-svn: 100031
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llvm-svn: 100016
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llvm-svn: 99975
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llvm-svn: 99974
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llvm-svn: 99954
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Since it is just a pxor in disguise, we should probably expand it to a full
polymorphic triple.
llvm-svn: 99953
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SSEDomainFix will collapse to the domain with the lower number when it has a
choice. The SSEPackedSingle domain often has smaller instructions, so prefer
that.
llvm-svn: 99952
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llvm-svn: 99948
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Not running 'make check-all' before committing is a bad idea.
llvm-svn: 99933
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llvm-svn: 99931
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memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.
llvm-svn: 99928
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llvm-svn: 99916
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Rewrite the pmulld patterns, and make sure that they fold in loads of
arguments into the instruction.
llvm-svn: 99910
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create symbols. It is extremely error prone and a source of a lot
of the remaining integrated assembler bugs on x86-64.
This fixes rdar://7807601.
llvm-svn: 99902
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to be fixed any time soon.
llvm-svn: 99888
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MCContext. There is still one leak left in PIC16Section (the Items vector).
llvm-svn: 99887
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llvm-svn: 99859
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llvm-svn: 99855
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Cross-block inference is primitive and wrong, but the pass is working otherwise.
llvm-svn: 99848
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makes calls a little bit more consistent and allows easy removal of the
specializations in the future. Convert all callers to the templated functions.
llvm-svn: 99838
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the SDNodes.
llvm-svn: 99835
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Most of these were unused, some of them were wrong and unused (isS16Constant<short>,
isS10Constant<short>).
llvm-svn: 99827
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"the bigstack patch for SPU, with testcase. It is essentially the patch committed as 97091, and reverted as 97099, but with the following additions:
-in vararg handling, registers are marked to be live, to not confuse the register scavenger
-function prologue and epilogue are not emitted, if the stack size is 16. 16 means it is empty - there is only the register scavenger emergency spill slot, which is not used as there is no stack."
llvm-svn: 99819
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llvm-svn: 99815
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These instructions use byte index in a control vector (M:Vm) to lookup byte
values in a table and generate a new vector (D:Vd). The table is specified via
a list of vectors, which can be:
{Dn}
{Dn D<n+1>}
{Dn D<n+1> D<n+2>}
{Dn D<n+1> D<n+2> D<n+3>}
llvm-svn: 99789
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llvm-svn: 99770
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llvm-svn: 99760
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matchable: it seems like it would always constant fold.
llvm-svn: 99758
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this also depends on the new "bitconvert dropping" behavior just
added to tblgen.
llvm-svn: 99757
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llvm-svn: 99755
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input to be v8i8 or v16i8, which buildvectors get canonicalized to.
This allows the patterns that were previously using a bare 'vnot' to
match, before they couldn't.
llvm-svn: 99754
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patterns that would never match because of bitcast, and eliminating use
of vnot_conv.
llvm-svn: 99753
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llvm-svn: 99750
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*input* of other type, which is the VT.
llvm-svn: 99749
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llvm-svn: 99748
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llvm-svn: 99743
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their flags correctly.
llvm-svn: 99738
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llvm-svn: 99737
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nodes all have an EFLAGS result when made by isel lowering.
llvm-svn: 99736
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llvm-svn: 99705
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llvm-svn: 99704
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llvm-svn: 99700
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it as the format for the appropriate N3V*SL*<> classes. These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.
Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):
vmlal.s32 q3, d2, d10[0]
llvm-svn: 99690
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