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* [SystemZ] Add floating-point test data class instructions.Marcin Koscielnicki2016-06-295-0/+29
| | | | | | | These are not used by CodeGen yet - ISD combiners creating the new node will come in subsequent patches. llvm-svn: 274108
* [ARM] Fix 28282: cost computation for constant hoistingWeiming Zhao2016-06-281-1/+1
| | | | | | | | | | | | | | | | | Summary: This fixes bug: https://llvm.org/bugs/show_bug.cgi?id=28282 Currently the cost model of constant hoisting checks the bit width of the data type of the constants. However, the actual immediate value is small enough and not need to be hoisted. This patch checks for the actual bit width needed for the constant. Reviewers: t.p.northover, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D21668 llvm-svn: 274073
* Relax the clearance calculating for breaking partial register dependency.Dehao Chen2016-06-281-6/+16
| | | | | | | | | | | | Summary: LLVM assumes that large clearance will hide the partial register spill penalty. But in our experiment, 16 clearance is too small. As the inserted XOR is normally fairly cheap, we should have a higher clearance threshold to aggressively insert XORs that is necessary to break partial register dependency. Reviewers: wmi, davidxl, stoklund, zansari, myatsina, RKSimon, DavidKreitzer, mkuper, joerg, spatel Subscribers: davidxl, llvm-commits Differential Revision: http://reviews.llvm.org/D21560 llvm-svn: 274068
* [SystemZ] Use NILL instruction instead of NILF where possibleZhan Jun Liau2016-06-281-1/+32
| | | | | | | | | | | | | | | | | | | Summary: SystemZ shift instructions only use the last 6 bits of the shift amount. When the result of an AND operation is used as a shift amount, this means that we can use the NILL instruction (which operates on the last 16 bits) rather than NILF (which operates on the last 32 bits) for a 16-bit savings in instruction size. Reviewers: uweigand Subscribers: llvm-commits Author: colpell Committing on behalf of Elliot. Differential Revision: http://reviews.llvm.org/D21686 llvm-svn: 274066
* X86FrameLowering: Check subregs when deciding prolog kill flagsMatthias Braun2016-06-281-3/+15
| | | | llvm-svn: 274057
* Use isPositionIndependent in a few more places.Rafael Espindola2016-06-282-5/+4
| | | | | | | | | I think this converts all the simple cases that really just care about the generated code being position independent or not. The remaining uses are a bit more complicated and are checking things like "is this a library or executable" or "can this symbol be preempted". llvm-svn: 274055
* AMDGPU: Fix global isel crashesMatt Arsenault2016-06-282-6/+9
| | | | llvm-svn: 274039
* [X86] Reorder source list alphabetically. NFC.Michael Kuperstein2016-06-281-4/+4
| | | | llvm-svn: 274036
* AMDGPU: Fix typoMatt Arsenault2016-06-281-7/+6
| | | | llvm-svn: 274034
* AMDGPU: Remove unused functionMatt Arsenault2016-06-282-33/+0
| | | | llvm-svn: 274033
* [X86] Make WRPKRU/RDPKRU pass -verify-machineinstrsDavid Majnemer2016-06-281-9/+6
| | | | | | | | | | | The original implementation attempted to zero registers using XOR %foo, %foo. This is problematic because it constitutes a read-modify-write of a register which might not be defined. Instead, use MOV32r0 to avoid these problems; expandPostRAPseudo does the right thing here. llvm-svn: 274024
* Don't pass a Reloc::Model to GVIsIndirectSymbol.Rafael Espindola2016-06-287-19/+10
| | | | | | | | It already has access to it. While at it, rename it to isGVIndirectSymbol. llvm-svn: 274023
* Don't pass Reloc::Model to places that already have it. NFC.Rafael Espindola2016-06-288-36/+31
| | | | llvm-svn: 274022
* Convert more cases to isPositionIndependent(). NFC.Rafael Espindola2016-06-289-22/+22
| | | | llvm-svn: 274021
* Delete dead code. NFC.Rafael Espindola2016-06-283-12/+8
| | | | llvm-svn: 274020
* [SystemZ] Save/restore r6 and r7 if function contains landing pad.Marcin Koscielnicki2016-06-281-0/+6
| | | | | | | | This fixes PR27102. Differential Revision: http://reviews.llvm.org/D18541 llvm-svn: 274017
* [X86][AVX] Peek through bitcasts to find the source of broadcasts (reapplied)Simon Pilgrim2016-06-281-3/+27
| | | | | | | | | | | | | | AVX1 can only broadcast vectors as floats/doubles, so for 256-bit vectors we insert bitcasts if we are shuffling v8i32/v4i64 types. Unfortunately the presence of these bitcasts prevents the current broadcast lowering code from peeking through cases where we have concatenated / extracted vectors to create the 256-bit vectors. This patch allows us to peek through bitcasts as long as the number of elements doesn't change (i.e. element bitwidth is the same) so the broadcast index is not affected. Note this bitcast peek is different from the stage later on which doesn't care about the type and is just trying to find a load node. As we're being more aggressive with bitcasts, we also need to ensure that the broadcast type is correctly bitcasted Differential Revision: http://reviews.llvm.org/D21660 llvm-svn: 274013
* Convert 2 more uses to shouldAssumeDSOLocal(). NFC.Rafael Espindola2016-06-282-4/+4
| | | | llvm-svn: 274009
* Use isPositionIndependent(). NFC.Rafael Espindola2016-06-281-2/+1
| | | | llvm-svn: 274005
* [X86][SSE] Added support for combining target shuffles to ↵Simon Pilgrim2016-06-281-5/+101
| | | | | | | | | | | | (V)PSHUFD/VPERMILPD/VPERMILPS immediate permutes This patch allows target shuffles to be combined to single input immediate permute instructions - (V)PSHUFD/VPERMILPD/VPERMILPS - allowing more general pattern matching than what we current do and improves the likelihood of memory folding compared to existing patterns which tend to reuse the input in multiple arguments. Further permute instructions (V)PSHUFLW/(V)PSHUFHW/(V)PERMQ/(V)PERMPD may be added in the future but its proven tricky to create tests cases for them so far. (V)PSHUFLW/(V)PSHUFHW is already handled quite well in combineTargetShuffle so it may be that removing some of that code may allow us to perform more of the combining in one place without duplication. Differential Revision: http://reviews.llvm.org/D21148 llvm-svn: 273999
* NFC. Fix popular typo in comment 'deferencing' --> 'dereferencing'.Nick Lewycky2016-06-283-9/+9
| | | | | | Bonus changes, * placement in X86ISelLowering and 'exerce' -> 'exercise' in test. llvm-svn: 273984
* AMDGPU: Fix out of bounds indirect indexing errorsMatt Arsenault2016-06-281-8/+19
| | | | | | | This was producing acceses to registers beyond the super register's limits, resulting in verifier failures. llvm-svn: 273977
* AArch64: Remove unnecessary namespace llvm; NFCMatthias Braun2016-06-281-4/+0
| | | | llvm-svn: 273975
* AMDGPU: Fix global isel buildMatt Arsenault2016-06-282-15/+15
| | | | llvm-svn: 273964
* Fix typo.Rafael Espindola2016-06-271-1/+1
| | | | | | Thanks to Benjamin Kramer for noticing. llvm-svn: 273959
* Move shouldAssumeDSOLocal to Target.Rafael Espindola2016-06-2712-31/+60
| | | | | | Should fix the shared library build. llvm-svn: 273958
* [Sparc] Atomics pass changes to make work with SparcV8 back-ends.Chris Dewhurst2016-06-271-4/+2
| | | | | | This change reverts a "false" test that was placed to avoid regressions while the atomics pass was completed for the Sparc back-ends. llvm-svn: 273949
* AMDGPU: Set MinInstAlignmentMatt Arsenault2016-06-271-0/+1
| | | | | | Not sure this actually changes anything llvm-svn: 273947
* Convert a few more comparisons to isPositionIndependent(). NFC.Rafael Espindola2016-06-275-7/+9
| | | | llvm-svn: 273945
* Delete the IsStatic predicate.Rafael Espindola2016-06-272-7/+6
| | | | | | In all its uses it was equivalent to IsNotPIC. llvm-svn: 273943
* AMDGPU: Implement per-function subtargetsMatt Arsenault2016-06-274-42/+76
| | | | llvm-svn: 273940
* AMDGPU: Move subtarget feature checks into passesMatt Arsenault2016-06-276-28/+37
| | | | llvm-svn: 273937
* Only emit extension for zeroext/signext arguments if type is < 32 bitsJustin Holewinski2016-06-271-2/+2
| | | | | | | | | | Reviewers: jingyue, jlebar Subscribers: jholewinski Differential Revision: http://reviews.llvm.org/D21756 llvm-svn: 273922
* Teach shouldAssumeDSOLocal about tls.Rafael Espindola2016-06-271-10/+8
| | | | | | Fixes a fixme about handling other visibilities. llvm-svn: 273921
* AMDGPU: Fix verifier errors with undef vector indicesMatt Arsenault2016-06-271-27/+37
| | | | | | Also fix pointlessly adding exec to liveins. llvm-svn: 273916
* Use isPositionIndependent(). NFC.Rafael Espindola2016-06-271-2/+2
| | | | llvm-svn: 273907
* Use isPositionIndependent(). NFC.Rafael Espindola2016-06-272-5/+3
| | | | llvm-svn: 273903
* Refactor duplicated condition.Rafael Espindola2016-06-271-4/+3
| | | | llvm-svn: 273900
* X86 Lowering - Fixed a crash in ICMP scalar instructionElena Demikhovsky2016-06-271-4/+2
| | | | | | | | Fixed a bug in EmitTest() function in combining shl + icmp. https://llvm.org/bugs/show_bug.cgi?id=28119 llvm-svn: 273899
* Use isPositionIndependent(). NFC.Rafael Espindola2016-06-271-3/+2
| | | | llvm-svn: 273896
* [SystemZ] Avoid generating 2 XOR instructions for (and (xor x, -1), y)Zhan Jun Liau2016-06-271-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Created a pattern to match 64-bit mode (and (xor x, -1), y) to a shorter sequence of instructions. Before the change, the canonical form is translated to: xihf %r3, 4294967295 xilf %r3, 4294967295 ngr %r2, %r3 After the change, the canonical form is translated to: ngr %r3, %r2 xgr %r2, %r3 Reviewers: zhanjunl, uweigand Subscribers: llvm-commits Author: assem Committing on behalf of Assem. Differential Revision: http://reviews.llvm.org/D21693 llvm-svn: 273887
* [Hexagon] Equally-sized vectors are equivalent in ISel (except vNi1)Krzysztof Parzyszek2016-06-272-52/+24
| | | | llvm-svn: 273885
* [mips] Add instruction itineraries for LSA, DLSASimon Dardis2016-06-271-7/+6
| | | | | | | | Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D21679 llvm-svn: 273883
* Revert 273848, it caused PR28329Nico Weber2016-06-271-7/+0
| | | | llvm-svn: 273879
* Last line of file missing on previous check-in.Chris Dewhurst2016-06-271-0/+1
| | | | llvm-svn: 273878
* Move isPositionIndependent up to AsmPrinter.Rafael Espindola2016-06-273-8/+3
| | | | | | Use it in ppc too. llvm-svn: 273877
* [Sparc] Formatting and commenting changes per review.Chris Dewhurst2016-06-272-185/+191
| | | | | | Differential Review: http://reviews.llvm.org/rL273108 llvm-svn: 273876
* Use the isPositionIndependent predicate. NFC.Rafael Espindola2016-06-271-4/+2
| | | | llvm-svn: 273875
* [ARM] Use member initializers in ARMSubtarget. NFCIDiana Picus2016-06-272-103/+78
| | | | | | | | Same as r273556, but with C++11 member initializers. Change suggested by Matthias Braun (see http://reviews.llvm.org/D21432). llvm-svn: 273873
* Fix "not all control paths return a value" warning on MSVCSimon Pilgrim2016-06-271-0/+2
| | | | llvm-svn: 273872
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