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* allow tests to run on powerpc-darwin8 again, checking for __ppc__David Fang2013-07-241-2/+2
| | | | llvm-svn: 187027
* Split generated asm mnemonic matching table into a separate table for each ↵Craig Topper2013-07-245-1/+5
| | | | | | | | asm variant. This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o. llvm-svn: 187026
* Revert accidental commit.Craig Topper2013-07-241-1/+1
| | | | llvm-svn: 187021
* Fix aliases for shrd/shld to handle Intel syntax properly. Also suppress ↵Craig Topper2013-07-242-14/+14
| | | | | | them from being used by the asm printer. llvm-svn: 187020
* DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)FreeTom Stellard2013-07-232-0/+17
| | | | | | | This commit also implements these functions for R600 and removes a test case that was relying on the buggy behavior. llvm-svn: 187007
* R600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS loads when necessaryTom Stellard2013-07-232-19/+7
| | | | | | | | | | These are really the same address space in hardware. The only difference is that CONSTANT_ADDRESS uses a special cache for faster access. When we are unable to use the constant kcache for some reason (e.g. smaller types or lack of indirect addressing) then the instruction selector must use GLOBAL_ADDRESS loads instead. llvm-svn: 187006
* [ARM][ISel] Improve the lowering of vector loads.Quentin Colombet2013-07-231-1/+3
| | | | | | | | | | | | | | | | When vectors are built from a single value, the ARM lowering issues a scalar_to_vector node. This node is then always morphed into a move from the general purpose unit to the vector unit. When the value comes from a load, this can be simplified into a vector load to the right lane. This patch changes the lowering of insert_vector_elt to expose a vector friendly pattern in this situation. This is a step toward fixing <rdar://problem/14170854>. llvm-svn: 186999
* Remove some errant space charcters in mnemonic strings.Craig Topper2013-07-232-12/+12
| | | | llvm-svn: 186932
* Don't let x86 asm printer use the no operand movsd alias. It should use the ↵Craig Topper2013-07-231-1/+1
| | | | | | normal movsl instead. llvm-svn: 186924
* R600: Add support for 24-bit MAD instructionsTom Stellard2013-07-232-2/+12
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186923
* R600: Add support for 24-bit MUL instructionsTom Stellard2013-07-234-5/+75
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186922
* R600: Improve support for < 32-bit loadsTom Stellard2013-07-234-11/+39
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186921
* R600: Rename AMDILISelDAGToDAG.cpp -> AMDGPUISelDAGToDAG.cppTom Stellard2013-07-232-1/+1
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186920
* R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel::Select()Tom Stellard2013-07-234-49/+160
| | | | | | | | | | This increases the number of opportunites we have for folding. With the previous implementation we were unable to fold into any instructions other than the first when multiple instructions were selected from a single SDNode. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186919
* R600: Use KCache for kernel argumentsTom Stellard2013-07-234-49/+22
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186918
* R600: Simplify assembly for KCache registers using the TableGen !add operatorTom Stellard2013-07-231-4/+4
| | | | | | | | | | | | | Before: MOV * T0.W, KC0[131-128].Y After: MOV * T0.W, KC0[3].Y Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186917
* R600: Use the same compute kernel calling convention for all GPUsTom Stellard2013-07-233-11/+27
| | | | | | | | A side-effect of this is that now the compiler expects kernel arguments to be 4-byte aligned. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186916
* R600: Use correct LoadExtType when lowering kernel argumentsTom Stellard2013-07-231-1/+9
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186915
* R600: Clean up extended load patternsTom Stellard2013-07-234-15/+31
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186914
* R600: Expand vector FNEGTom Stellard2013-07-231-0/+3
| | | | llvm-svn: 186913
* Revert r186907 to fix bots.Craig Topper2013-07-231-1/+1
| | | | llvm-svn: 186910
* Don't let x86 asm printer use the no operand movsd alias. It should use the ↵Craig Topper2013-07-231-1/+1
| | | | | | normal movsl instead. llvm-svn: 186907
* Add aliases to map 'imm, mem' form of x86 bts/btr/btc without a size suffix ↵Craig Topper2013-07-231-0/+7
| | | | | | | | to their 32-bit forms. This makes them consistent with 'bt' which already had this handling. gas has the same behavior. There have been discussions on the mailing list about determining size based on the immediate, but my goal here was just to remove the inconsistency. llvm-svn: 186904
* Explicitly don't let the asm printer use the clrb/w/l aliases for xor %reg, ↵Craig Topper2013-07-231-4/+4
| | | | | | | | %reg. It only didn't use it before because it seems InstAlias handling in the asm printer fails to count tied operands so it tried to find an xor with 2 operands instead of the 3 it wfails to count tied. llvm-svn: 186900
* Suppress argumentless aliases for some x86 FP operations from being used by ↵Craig Topper2013-07-231-14/+14
| | | | | | the asm writer. Prefer to use the explicit %st(1) form. llvm-svn: 186897
* Fix the move to/from accumulator register instructions that use a full 64-bitKevin Enderby2013-07-222-15/+34
| | | | | | | | absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 llvm-svn: 186878
* Recommit r186813: More Intel syntax alias fixes. With the addition of ↵Craig Topper2013-07-221-28/+28
| | | | | | suppressing some of the aliases from being emitted by the asm printer. llvm-svn: 186869
* [mips] Fix MipsAsmParser::parseCCRRegs.Akira Hatanaka2013-07-221-17/+10
| | | | | | | | Enable parsing all 32 floating point control registers $0-31 and stop trying to parse floating point condition code register $fcc0. Also, return ParseFail if the operand being parsed is not in the expected format. llvm-svn: 186861
* [mips] Use ADDu instead of OR to copy general purpose registers. Also, deleteAkira Hatanaka2013-07-223-12/+5
| | | | | | | the InstAlias pattern which maps "move" to OR to resolve ambiguity in MatchTable. llvm-svn: 186855
* [NVPTX] Remove unused prototypesJustin Holewinski2013-07-221-3/+0
| | | | llvm-svn: 186844
* This adds range checking for "ldr Rn, [pc, #imm]" Thumb Mihai Popa2013-07-224-25/+62
| | | | | | | | | | instructions. With this patch: 1. ldr.n is recognized as mnemonic for the short encoding 2. ldr.w is recognized as menmonic for the long encoding 3. ldr will map to either short or long encodings depending on the size of the offset llvm-svn: 186831
* [NVPTX] Use approximate FP ops when unsafe-fp-math is used, and appendJustin Holewinski2013-07-223-56/+61
| | | | | | .ftz to instructions if the nvptx-f32ftz attribute is set to "true" llvm-svn: 186820
* Revert "More Intel syntax alias fixes."Tim Northover2013-07-221-28/+28
| | | | | | This reverts commit r186813, which broke the bots. llvm-svn: 186818
* Fix typo. Change %cl to CL in Intel pattern.Craig Topper2013-07-221-1/+1
| | | | llvm-svn: 186815
* More Intel syntax alias fixes.Craig Topper2013-07-223-19/+19
| | | | llvm-svn: 186814
* More Intel syntax alias fixes.Craig Topper2013-07-221-28/+28
| | | | llvm-svn: 186813
* Change %xmm0 to XMM0 in Intel side of asm strings for PBLENDVB.Craig Topper2013-07-221-6/+6
| | | | llvm-svn: 186812
* Add Intel variants to aliases for some FP instructions.Craig Topper2013-07-221-8/+8
| | | | llvm-svn: 186811
* ARM: remove now unneeded custom Asm convertersTim Northover2013-07-224-415/+16
| | | | | | | | After Ulrich's r180677 (thanks!) TableGen is intelligent enough to handle tied constraints involving complex operands properly, so virtually all of the ARM custom converters are now unnecessary. llvm-svn: 186810
* Reverse operands for Intel syntax form of 'bt' alias.Craig Topper2013-07-221-1/+2
| | | | llvm-svn: 186809
* Treat nothrow forms of ::operator delete and ::operator delete[] asRichard Smith2013-07-211-0/+2
| | | | | | deallocation functions. llvm-svn: 186798
* Mark that the _ftol2 function used by windows on x86 to handle fptoui ↵Craig Topper2013-07-212-3/+5
| | | | | | modifies ECX. llvm-svn: 186787
* Refactor AnalyzeBranch on ARM. The previous version did not always analyzeLang Hames2013-07-191-88/+67
| | | | | | | | | | | | | | | | | | indirect branches correctly. Under some circumstances, this led to the deletion of basic blocks that were the destination of indirect branches. In that case it left indirect branches to nowhere in the code. This patch replaces, and is more general than either of the previous fixes for indirect-branch-analysis issues, r181161 and r186461. For other branches (not indirect) this refactor should have *almost* identical behavior to the previous version. There are some corner cases where this refactor is able to analyze blocks that the previous version could not (e.g. this necessitated the update to thumb2-ifcvt2.ll). <rdar://problem/14464830> llvm-svn: 186735
* R600: Don't emit empty then clause and use alu_pop_afterVincent Lejeune2013-07-193-11/+46
| | | | llvm-svn: 186725
* R600: Simplify AMDILCFGStructurize by removing templates and assuming single ↵Vincent Lejeune2013-07-193-2494/+1324
| | | | | | exit llvm-svn: 186724
* R600: Replace legacy debug code in AMDILCFGStructurizer.cppVincent Lejeune2013-07-191-228/+235
| | | | llvm-svn: 186723
* Add a line that got missed off somehow. Sorry about that!Joey Gouly2013-07-191-0/+1
| | | | llvm-svn: 186692
* [SystemZ] Add ALRK, AGLRK, SLRK and SGLRKRichard Sandiford2013-07-191-4/+10
| | | | | | | Follows the same lines as r186686, but much more limited, since we only use ADD LOGICAL for multi-i64 additions. llvm-svn: 186689
* [ARMv8] Implement the NEON instructions VRINT{N, X, A, Z, M, P}.Joey Gouly2013-07-192-0/+58
| | | | llvm-svn: 186688
* [SystemZ] Add AHIK and AGHIKRichard Sandiford2013-07-192-2/+37
| | | | | | | I did these as a separate patch because it uses a slightly different form of RIE layout. llvm-svn: 186687
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