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* R600/SI: improve post ISel foldingChristian Konig2013-03-261-31/+43
| | | | | | | Not only fold immediates, but avoid unnecessary copies as well. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178024
* R600/SI: improve vector interpolationChristian Konig2013-03-261-0/+20
| | | | | | | Prevent loading M0 multiple times. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178023
* R600/SI: avoid unecessary subreg extraction in IMAGE_SAMPLEChristian Konig2013-03-262-14/+8
| | | | | | | Just define the address as unknown instead of VReg_32. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178022
* R600/SI: switch back to RegPressure schedulingChristian Konig2013-03-263-1/+9
| | | | | Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178021
* R600/SI: mark most intrinsics as readnone v2Christian Konig2013-03-261-5/+5
| | | | | | | | | They read from constant register space anyway. v2: fix lit tests Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178020
* R600/SI: replace WQM intrinsicChristian Konig2013-03-265-28/+14
| | | | | | | Just enable WQM when we see an LDS interpolation instruction. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178019
* R600/SI: fix ELSE pseudo op handlingChristian Konig2013-03-261-1/+2
| | | | | | | | | | | Restore the EXEC mask early, otherwise a copy might end up not beeing executed. Candidate for the mesa stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178018
* Patch by Gordon Keiser!Joe Abbey2013-03-261-1/+1
| | | | | | | | | | If PC or SP is the destination, the disassembler erroneously failed with the invalid encoding, despite the manual saying that both are fine. This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a postindexed load, where the offset 0xc is applied to SP after the load occurs. llvm-svn: 178017
* PowerPC: Mark patterns as isCodeGenOnly.Ulrich Weigand2013-03-264-7/+21
| | | | | | | | | | | There remain a number of patterns that cannot (and should not) be handled by the asm parser, in particular all the Pseudo patterns. This commit marks those patterns as isCodeGenOnly. No change in generated code. llvm-svn: 178008
* PowerPC: Simplify handling of fixups.Ulrich Weigand2013-03-264-70/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MCTargetDesc/PPCMCCodeEmitter.cpp current has code like: if (isSVR4ABI() && is64BitMode()) Fixups.push_back(MCFixup::Create(0, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_toc16)); else Fixups.push_back(MCFixup::Create(0, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_lo16)); This is a problem for the asm parser, since it requires knowledge of the ABI / 64-bit mode to be set up. However, more fundamentally, at this point we shouldn't make such distinctions anyway; in an assembler file, it always ought to be possible to e.g. generate TOC relocations even when the main ABI is one that doesn't use TOC. Fortunately, this is actually completely unnecessary; that code was added to decide whether to generate TOC relocations, but that information is in fact already encoded in the VariantKind of the underlying symbol. This commit therefore merges those fixup types into one, and then decides which relocation to use based on the VariantKind. No changes in generated code. llvm-svn: 178007
* PowerPC: Simplify FADD in round-to-zero mode.Ulrich Weigand2013-03-264-101/+50
| | | | | | | | | | | | | | | | | | | | | | | As part of the the sequence generated to implement long double -> int conversions, we need to perform an FADD in round-to-zero mode. This is problematical since the FPSCR is not at all modeled at the SelectionDAG level, and thus there is a risk of getting floating point instructions generated out of sequence with the instructions to modify FPSCR. The current code handles this by somewhat "special" patterns that in part have dummy operands, and/or duplicate existing instructions, making them awkward to handle in the asm parser. This commit changes this by leaving the "FADD in round-to-zero mode" as an atomic operation on the SelectionDAG level, and only split it up into real instructions at the MI level (via custom inserter). Since at *this* level the FPSCR *is* modeled (via the "RM" hard register), much of the "special" stuff can just go away, and the resulting patterns can be used by the asm parser. No significant change in generated code expected. llvm-svn: 178006
* PowerPC: Remove LDrs pattern.Ulrich Weigand2013-03-263-16/+9
| | | | | | | | | | | | | | | | | | | | The LDrs pattern is a duplicate of LD, except that it accepts memory addresses where the displacement is a symbolLo64. An operand type "memrs" is defined for just that purpose. However, this wouldn't be necessary if the default "memrix" operand type were to simply accept 64-bit symbolic addresses directly. The only problem with that is that it uses "symbolLo", which is hardcoded to 32-bit. To fix this, this commit changes "memri" and "memrix" to use new operand types for the memory displacement, which allow iPTR instead of i32. This will also make address parsing easier to implment in the asm parser. No change in generated code. llvm-svn: 178005
* PowerPC: Remove ADDIL patterns.Ulrich Weigand2013-03-264-20/+13
| | | | | | | | | | | | | | The ADDI/ADDI8 patterns are currently duplicated into ADDIL/ADDI8L, which describe the same instruction, except that they accept a symbolLo[64] operand instead of a s16imm[64] operand. This duplication confuses the asm parser, and it actually not really needed, since symbolLo[64] already accepts immediate operands anyway. So this commit removes the duplicate patterns. No change in generated code. llvm-svn: 178004
* PowerPC: Use CCBITRC operand for ISEL patterns.Ulrich Weigand2013-03-265-46/+19
| | | | | | | | | | | | This commit changes the ISEL patterns to use a CCBITRC operand instead of a "pred" operand. This matches the actual instruction text more directly, and simplifies use of ISEL with the asm parser. In addition, this change allows some simplification of handling the "pred" operand, as this is now only used by BCC. No change in generated code. llvm-svn: 178003
* PowerPC: Simplify BLR pattern.Ulrich Weigand2013-03-263-12/+6
| | | | | | | | | | | | | | | | | The BLR pattern cannot be recognized by the asm parser in its current form. This complexity is due to an apparent attempt to enable conditional BLR variants. However, none of those can ever be generated by current code; the pattern is only ever created using the default "pred" operand. To simplify the pattern and allow it to be recognized by the parser, this commit removes those attempts at conditional BLR support. When we later come back to actually add real conditional BLR, this should probably be done via a fully generic conditional branch pattern. No change in generated code. llvm-svn: 178002
* PowerPC: Move some 64-bit branch patterns.Ulrich Weigand2013-03-261-17/+18
| | | | | | | | | | | | In PPCInstr64Bit.td, some branch patterns appear in a different sequence than the corresponding 32-bit patterns in PPCInstrInfo.td. To simplify future changes that affect both files, this commit moves those patterns to rearrange them into a similar sequence. No effect on generated code. llvm-svn: 178001
* R600: fix DenseMap with pointer key iteration in the structurizerChristian Konig2013-03-261-2/+4
| | | | | | | | | Use a MapVector on types where the iteration order matters. Otherwise we doesn't always produce a deterministic output. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 177999
* ARM Scheduler Model: Add resources instructions, map resources in subtargetsArnold Schwaighofer2013-03-264-24/+70
| | | | | | | | Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. llvm-svn: 177968
* ARM Scheduler Model: Partial implementation of the new machine scheduler modelArnold Schwaighofer2013-03-261-0/+57
| | | | | | | | | | This is very much work in progress. Please send me a note if you start to depend on the added abstract read/write resources. They are subject to change until further notice. The old itinerary is still the default. llvm-svn: 177967
* Revise alignment checking/calculation on 256-bit unaligned memory accessMichael Liao2013-03-251-7/+6
| | | | | | | | | - It's still considered aligned when the specified alignment is larger than the natural alignment; - The new alignment for the high 128-bit vector should be min(16, alignment) as the pointer is advanced by 16, a power-of-2 offset. llvm-svn: 177947
* Add a scheduling model for Intel Sandy Bridge microarchitecture.Jakob Stoklund Olesen2013-03-251-0/+123
| | | | | | | The model isn't hooked up by this patch because the instruction set isn't fully annotated yet. llvm-svn: 177942
* Remove IIC_DEFAULT from X86Schedule.tdJakob Stoklund Olesen2013-03-255-78/+76
| | | | | | | | All the instructions tagged with IIC_DEFAULT had nothing in common, and we already have a NoItineraries class to represent untagged instructions. llvm-svn: 177937
* Annotate X86InstrCompiler.td with SchedRW lists.Jakob Stoklund Olesen2013-03-251-10/+20
| | | | llvm-svn: 177936
* Annotate shifts and rotates with SchedRW lists.Jakob Stoklund Olesen2013-03-251-17/+37
| | | | llvm-svn: 177935
* X86DisassemblerDecoder.c: Make this C89-compliant.NAKAMURA Takumi2013-03-251-1/+1
| | | | llvm-svn: 177910
* Whitespace.NAKAMURA Takumi2013-03-251-160/+160
| | | | llvm-svn: 177909
* Fix comment.Akira Hatanaka2013-03-251-3/+3
| | | | llvm-svn: 177899
* Use direct types in PowerPC instruction patterns.Ulrich Weigand2013-03-252-270/+262
| | | | | | | | | | This commit updates the PowerPC back-end (PPCInstrInfo.td and PPCInstr64Bit.td) to use types instead of register classes in instruction patterns, along the lines of Jakob Stoklund Olesen's changes in r177835 for Sparc. llvm-svn: 177890
* Use direct types in PowerPC Pat patterns.Ulrich Weigand2013-03-252-113/+113
| | | | | | | | | This commit updates the PowerPC back-end (PPCInstrInfo.td and PPCInstr64Bit.td) to use types instead of register classes in Pat patterns, along the lines of Jakob Stoklund Olesen's changes in r177829 for Sparc. llvm-svn: 177889
* x86 -- add the XTEST instructionDave Zarzycki2013-03-254-31/+30
| | | | llvm-svn: 177888
* x86 -- disassemble the REP/REPNE prefix when neededDave Zarzycki2013-03-251-7/+20
| | | | | | This fixes Apple bug: 13493622 llvm-svn: 177887
* Remove assert. There may be target-dependent attributes left.Bill Wendling2013-03-251-1/+0
| | | | llvm-svn: 177878
* [arm load/store optimizer] When trying to merge a base update load/store, makeChad Rosier2013-03-251-1/+1
| | | | | | | | | | | sure the base register and would-be writeback register don't conflict for stores. This was already being done for loads. Unfortunately, it is rather difficult to create a test case for this issue. It was exposed in 450.soplex at LTO and requires unlucky register allocation. <rdar://13394908> llvm-svn: 177874
* [NVPTX] Fix handling of vector argumentsJustin Holewinski2013-03-242-7/+56
| | | | llvm-svn: 177847
* Clean up Sparc patterns.Jakob Stoklund Olesen2013-03-241-5/+5
| | | | | | | The types of register variables no longer need to be specified in output patterns. llvm-svn: 177845
* Give Sparc instruction patterns direct types instead of register classes.Jakob Stoklund Olesen2013-03-241-81/+68
| | | | | | | Also update the documentation since Sparc is the nicest backend, and used as an example in WritingAnLLVMBackend. llvm-svn: 177835
* PPC ZERO register needs a register number of 0.Hal Finkel2013-03-231-0/+1
| | | | | | | | | In order for the new ZERO register to be used with MC, etc. we need to specify its register number (0). Thanks to Kai for reporting the problem! llvm-svn: 177833
* Note in PPCFunctionInfo VRSAVE spillsHal Finkel2013-03-234-14/+34
| | | | | | | | | | | | In preparation for using the new register scavenger capability for providing more than one register simultaneously, specifically note functions that have spilled VRSAVE (currently, this can happen only in functions that use the setjmp intrinsic). As with CR spilling, such functions will need to provide two emergency spill slots to the scavenger. No functionality change intended. llvm-svn: 177832
* MCize the bcl instruction in PPCAsmPrinterHal Finkel2013-03-231-4/+5
| | | | | | | | | I recently added a BCL instruction definition as part of implementing SjLj support. This can also be used to MCize bcl emission in the asm printer. No functionality change intended. llvm-svn: 177830
* Use direct types in Sparc def : Pat patterns.Jakob Stoklund Olesen2013-03-231-10/+10
| | | | | | | | | | The SelectionDAG graph has MVT type labels, not register classes, so this makes it clearer what is happening. This notation is also robust against adding more types to the IntRegs register class. llvm-svn: 177829
* Cleanup some unused reg. scavenger parameters in PPCRegisterInfoHal Finkel2013-03-232-33/+19
| | | | | | | | | | | These spilling functions will eventually make use of the register scavenger, however, they'll do so by taking advantage of PEI's virtual-register-based delayed scavenging mechanism. As a result, these function parameters will not be used, and can be removed. No functionality change intended. llvm-svn: 177827
* Remove dead PPC LR spilling codeHal Finkel2013-03-231-30/+8
| | | | | | | | | | The LR register is unconditionally reserved, and its spilling and restoration is handled by the prologue/epilogue code. As a result, it is never explicitly spilled by the register allocator. No functionality change intended. llvm-svn: 177823
* Allow the register scavenger to spill multiple registersHal Finkel2013-03-227-7/+7
| | | | | | | | | | | | | | | | | | This patch lets the register scavenger make use of multiple spill slots in order to guarantee that it will be able to provide multiple registers simultaneously. To support this, the RS's API has changed slightly: setScavengingFrameIndex / getScavengingFrameIndex have been replaced by addScavengingFrameIndex / isScavengingFrameIndex / getScavengingFrameIndices. In forthcoming commits, the PowerPC backend will use this capability in order to implement the spilling of condition registers, and some special-purpose registers, without relying on r0 being reserved. In some cases, spilling these registers requires two GPRs: one for addressing and one to hold the value being transferred. llvm-svn: 177774
* Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and ↵Jyotsna Verma2013-03-225-494/+483
| | | | | | word. llvm-svn: 177747
* Remove ABI-duplicated call instruction patterns.Ulrich Weigand2013-03-228-148/+71
| | | | | | | | | | | | | | | | | | We currently have a duplicated set of call instruction patterns depending on the ABI to be followed (Darwin vs. Linux). This is a bit odd; while the different ABIs will result in different instruction sequences, the actual instructions themselves ought to be independent of the ABI. And in fact it turns out that the only nontrivial difference between the two sets of patterns is that in the PPC64 Linux ABI, the instruction used for indirect calls is marked to take X11 as extra input register (which is indeed used only with that ABI to hold an incoming environment pointer for nested functions). However, this does not need to be hard-coded at the .td pattern level; instead, the C++ code expanding calls can simply add that use, just like it adds uses for argument registers anyway. No change in generated code expected. llvm-svn: 177735
* Rename memrr ptrreg and offreg components.Ulrich Weigand2013-03-222-22/+22
| | | | | | | | | | | Currently, the sub-operand of a memrr address that corresponds to what hardware considers the base register is called "offreg", while the sub-operand that corresponds to the offset is called "ptrreg". To avoid confusion, this patch simply swaps the named of those two sub-operands and updates all uses. No functional change is intended. llvm-svn: 177734
* Fix swapped BasePtr and Offset in pre-inc memory addresses.Ulrich Weigand2013-03-224-20/+40
| | | | | | | | | | | | | | | | | | | | PPCTargetLowering::getPreIndexedAddressParts currently provides the base part of a memory address in the offset result, and the offset part in the base result. That swap is then undone again when an MI instruction is generated (in PPCDAGToDAGISel::Select for loads, and using .md Pat patterns for stores). This patch reverts this double swap, to make common code and back-end be in sync as to which part of the address is base and which is offset. To avoid performance regressions in certain cases, target code now checks whether the choice of base register would be rejected for pre-inc accesses by common code, and attempts to swap base and offset again in such cases. (Overall, this means that now pre-ice accesses are generated *more* frequently than before.) llvm-svn: 177733
* Tighten iaddroff ComplexPattern.Ulrich Weigand2013-03-221-4/+4
| | | | | | | | | | | | | | | | | The iaddroff ComplexPattern is supposed to recognize displacement expressions that have been processed by a SelectAddressRegImm, which means it needs to accept TargetConstant and TargetGlobalAddress nodes. Currently, it erroneously also accepts some other nodes, in particular Constant and PPCISD::Lo. While this problem is currently latent, it would cause wrong-code bugs with a follow-on patch I'm about to commit, so this patch tightens the ComplexPattern. The equivalent change is made in PPCDAGToDAGISel::Select, where pre-inc load patterns are handled (as opposed to store patterns, the loads are handled in C++ code without making use of the .td ComplexPattern). llvm-svn: 177732
* Remove the xaddroff ComplexPattern.Ulrich Weigand2013-03-223-31/+18
| | | | | | | | | The xaddroff pattern is currently (mistakenly) used to recognize the *base* register in pre-inc store patterns. This patch replaces those uses by ptr_rc_nor0 (as is elsewhere done to match the base register of an address), and removes the now unused ComplexPattern. llvm-svn: 177731
* R600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsicsMichel Danzer2013-03-224-15/+5
| | | | | | | | | | | | | | | | Fixes wrong lighting in some corner cases with r600g and radeonsi, e.g. manifested by failure of two piglit/glean tests and intermittent black patches in many apps. Tested on SI and RS880. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62012 [radeonsi] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58150 [r600g] NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 177730
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