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llvm-svn: 79483
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llvm-svn: 79443
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a smaller encoding. These kinds of patterns are very frequent in
sqlite3, for example.
llvm-svn: 79439
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llvm-svn: 79436
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This is derived from a patch by Anton Korzh. I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.
llvm-svn: 79428
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talk to the MCStreamer directly instead.
llvm-svn: 79405
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Add patterns and instruction encoding information.
Add custom lowering to deal with hardwired return register of
uncertain type (xmm0).
llvm-svn: 79377
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- Drop the Candidates argument and fix all callers. Now that RegScavenger
tracks available registers accurately, there is no need to restict the
search.
- Make sure that no aliases of the found register are in use. This was a potential bug.
llvm-svn: 79369
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llvm-svn: 79368
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llvm-svn: 79351
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llvm-svn: 79346
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on linux.
Patch by Dmitry Gorbachev!
llvm-svn: 79334
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really work anyway.
llvm-svn: 79321
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llvm-svn: 79318
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send instructions like:
NEW: movl "L___stack_chk_guard$non_lazy_ptr" - "L1$pb"(%esi), %eax
OLD: movl L___stack_chk_guard$non_lazy_ptr-"L1$pb"(%esi), %eax
through the streamer. Several fixmes.
llvm-svn: 79317
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returns a log2 value.
llvm-svn: 79293
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for a single "m" constraint; this is wrong because the
opcode of a load or store would have to change in parallel.
This patch makes it always compute addresses into a register,
which is correct but not as efficient as possible. 7144566.
llvm-svn: 79292
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TLOF is reinitialized with a different MCContext.
llvm-svn: 79253
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if not supported by the ELF subtarget.
llvm-svn: 79249
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just remove the argument and replace it with 1.
llvm-svn: 79246
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or some other situation where no xmm registers need to be saved.
llvm-svn: 79207
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llvm-svn: 79206
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after erasure.
llvm-svn: 79189
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llvm-svn: 79187
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llvm-svn: 79175
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we now
can asmprint:
NEW: movl "L___stack_chk_guard$non_lazy_ptr", %eax
OLD: movl L___stack_chk_guard$non_lazy_ptr, %eax
where 'new' is coming out of the MCInst version of the printer.
llvm-svn: 79170
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llvm-svn: 79167
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llvm-svn: 79165
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what was there before. In "no FP mode", we weren't generating labels and unwind
table entries after each "push" instruction. While more than likely "okay", it's
not technically correct. The major thing was that the ordering of when to define
a new CFA register and at what offset wasn't correct. This would cause the
exception handling to fail in ways most miserable to users.
I also cleaned up some code a bit. There's one function which has a "return" at
the beginning, so it's never used. Should I just remove it? :-)
llvm-svn: 79139
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llvm-svn: 79136
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llvm-svn: 79135
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support unaligned mem access only for certain types. (Should it be size
instead?)
ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.
llvm-svn: 79127
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is why they are datarel). This should fix PR4724, and is fallout
from r78890.
llvm-svn: 79111
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llvm-svn: 79107
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llvm-svn: 79101
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llvm-svn: 79098
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PIC16DebugInfo currently rely on NameStr of composite type descriptors to uniquely
identify debug info for two aggregate type decls with same name.
This implementation will change when we have MDNodes based debug info implemenatation in place
llvm-svn: 79097
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llvm-svn: 79094
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The Link Register is volatile when using the 32-bit SVR4 ABI.
Make it possible to use the 64-bit SVR4 ABI.
Add non-volatile registers for the 64-bit SVR4 ABI.
Make sure r2 is a reserved register when using the 64-bit SVR4 ABI.
Update PPCFrameInfo for the 64-bit SVR4 ABI.
Add FIXME for 64-bit Darwin PPC.
Insert NOP instruction after direct function calls.
Emit official procedure descriptors.
Create TOC entries for GlobalAddress references.
Spill 64-bit non-volatile registers to the correct slots.
Only custom lower VAARG when using the 32-bit SVR4 ABI.
Use simple VASTART lowering for the 64-bit SVR4 ABI.
llvm-svn: 79091
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llvm-svn: 79084
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llvm-svn: 79082
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the class it defines.
llvm-svn: 79081
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llvm-svn: 79080
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support for globals going into the appropriate sections with the flags.
This hopefully finishes unbreaking the previous behavior that I broke before.
llvm-svn: 79079
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them to null out the default section pointers.
llvm-svn: 79078
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class which represents the XCore cp/dp section flags. No functionality
change yet.
llvm-svn: 79077
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"the current basic block".
llvm-svn: 79069
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is frameless.
llvm-svn: 79067
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the register save area if %al is 0. This avoids touching xmm
regsiters when they aren't actually used.
llvm-svn: 79061
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-disable-fp-elim.
llvm-svn: 79039
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