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* Make X86's copyRegToReg able to handle copies to and from subclasses.Dan Gohman2009-04-201-20/+29
| | | | | | | This makes the extra copyRegToReg calls in ScheduleDAGSDNodesEmit.cpp unnecessary. Derived from a patch by Jakob Stoklund Olesen. llvm-svn: 69635
* Remove unused variable.Daniel Dunbar2009-04-201-1/+0
| | | | llvm-svn: 69624
* Move duplicated AddLiveIn function from X86 and ARM backends to be a methodBob Wilson2009-04-202-30/+8
| | | | | | | in the MachineFunction class, renaming it to addLiveIn for consistency with the same method in MachineBasicBlock. Thanks for Anton for suggesting this. llvm-svn: 69615
* Match C backend only if it explicitly requested.Devang Patel2009-04-201-2/+3
| | | | llvm-svn: 69613
* Emit the auto variables of a function into a different section than parameters.Sanjiv Gupta2009-04-202-24/+46
| | | | llvm-svn: 69605
* Fixed a few 64 bit cases in X86InstrInfo::commuteInstructionMon P Wang2009-04-181-3/+3
| | | | llvm-svn: 69417
* Recommit r69335 and r69336. These were not causing problems.Bill Wendling2009-04-171-3/+5
| | | | llvm-svn: 69394
* Move the AddLiveIn function definition closer to its uses.Bob Wilson2009-04-171-11/+11
| | | | llvm-svn: 69382
* Rearrange code to reduce indentation.Bob Wilson2009-04-171-41/+38
| | | | llvm-svn: 69381
* Clean up formatting, remove trailing whitespace, fix comment typos andBob Wilson2009-04-173-44/+31
| | | | | | punctuation. No functional changes. llvm-svn: 69378
* Use CallConvLower.h and TableGen descriptions of the calling conventionsBob Wilson2009-04-176-305/+561
| | | | | | for ARM. Patch by Sandeep Patel. llvm-svn: 69371
* For general dynamic TLS access we must useRafael Espindola2009-04-173-36/+32
| | | | | | | | | leaq foo@TLSGD(%rip), %rdi as part of the instruction sequence. Using a register other than %rdi and then copying it to %rdi is not valid. llvm-svn: 69350
* Revert r69335 and r69336. They were causing build failures.Bill Wendling2009-04-171-5/+3
| | | | llvm-svn: 69347
* MOV8rr_NOREX is a "Move" instruction. This doesn't currentlyDan Gohman2009-04-171-0/+1
| | | | | | | matter, because this instruction isn't generated until after things that care. llvm-svn: 69336
* Don't use MOV8rr_NOREX on x86-32. It doesn't actually hurt anything atDan Gohman2009-04-171-3/+4
| | | | | | present, but it's inconsistent. llvm-svn: 69335
* Fix some failures in targets on available_externally functions,Chris Lattner2009-04-173-0/+17
| | | | | | | this fixes a crash on CodeGen/Generic/externally_available.ll on ppc hosts. Thanks to Nicholas L for pointing this out. llvm-svn: 69333
* fix PR3995. A scale must be 1, 2, 4 or 8.Rafael Espindola2009-04-161-1/+1
| | | | llvm-svn: 69284
* Fix 80-column violations.Dan Gohman2009-04-152-3/+4
| | | | llvm-svn: 69204
* Add a folding table entry for MOV8rr_NOREX.Dan Gohman2009-04-151-0/+1
| | | | llvm-svn: 69203
* Fix X86MachineFunctionInfo's doxygen comment.Dan Gohman2009-04-151-2/+3
| | | | llvm-svn: 69127
* Do for GR16_NOREX what r69049 did for GR8_NOREX, to avoid trouble withDan Gohman2009-04-151-0/+35
| | | | | | the local register allocator. llvm-svn: 69115
* Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it whenDan Gohman2009-04-152-5/+20
| | | | | | | | either the source or destination is a physical h register. This fixes sqlite3 with the post-RA scheduler enabled. llvm-svn: 69111
* GR8_NOREX can contain the H registers, since they don't requireDan Gohman2009-04-151-2/+3
| | | | | | REX prefixes. llvm-svn: 69108
* For the h-register addressing-mode trick, use the correct value forDan Gohman2009-04-141-1/+14
| | | | | | any non-address uses of the address value. This fixes 186.crafty. llvm-svn: 69094
* Some of GR8_NOREX registers are only available in 64-bit mode.Evan Cheng2009-04-141-0/+48
| | | | llvm-svn: 69049
* Handle aggregate type arguments to direct and indirect calls.Sanjiv Gupta2009-04-144-35/+101
| | | | llvm-svn: 69022
* Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman2009-04-132-16/+16
| | | | | | | it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. llvm-svn: 68986
* Reapply 68847.Devang Patel2009-04-132-0/+4
| | | | | | Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default. llvm-svn: 68964
* Implement x86 h-register extract support.Dan Gohman2009-04-137-98/+359
| | | | | | | | | | | | | | | | | | | | | | | | - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. llvm-svn: 68962
* Remove x86's special-case handling for ISD::TRUNCATE andDan Gohman2009-04-131-85/+0
| | | | | | | | ISD::SIGN_EXTEND_INREG. Tablegen-generated code can handle these cases, and the scheduling issues observed earlier appear to be resolved now. llvm-svn: 68959
* Fix copy+pastos in comments.Dan Gohman2009-04-131-2/+2
| | | | llvm-svn: 68958
* List the l registers before h registers, for consistency.Dan Gohman2009-04-131-4/+4
| | | | llvm-svn: 68954
* Use X86::SUBREG_8BIT instead of hard-coding the equivalent constant.Dan Gohman2009-04-131-3/+3
| | | | llvm-svn: 68951
* Add a comment about MOVSX64rr8.Dan Gohman2009-04-131-0/+4
| | | | llvm-svn: 68950
* Fix another hard-coded constant to use X86AddrNumOperands.Dan Gohman2009-04-131-1/+1
| | | | | | This unbreaks the JIT on x86-64. llvm-svn: 68948
* X86-64 TLS support for local exec and initial exec.Rafael Espindola2009-04-133-10/+23
| | | | llvm-svn: 68947
* While passing arg of types larger than char only one byte at lower end was ↵Sanjiv Gupta2009-04-131-1/+1
| | | | | | getting passed. We couldn't catch this as we did not have tests that were passing an int value larger than 256. llvm-svn: 68946
* Add a new "available_externally" linkage type. This is intendedChris Lattner2009-04-131-0/+2
| | | | | | | | to support C99 inline, GNU extern inline, etc. Related bugzilla's include PR3517, PR3100, & PR2933. Nothing uses this yet, but it appears to work. llvm-svn: 68940
* In X86DAGToDAGISel::MatchWrapper, if base or index are set, avoid matchingRafael Espindola2009-04-121-3/+8
| | | | | | only if symbolic addresses are RIP relatives. llvm-svn: 68924
* refactor some code into X86DAGToDAGISel::MatchWrapperRafael Espindola2009-04-121-44/+51
| | | | llvm-svn: 68915
* fix a cross-block fastisel crash handling overflow intrinsics.Chris Lattner2009-04-121-5/+16
| | | | | | See comment for details. This fixes rdar://6772169 llvm-svn: 68890
* simplify code by using IntrinsicInst.Chris Lattner2009-04-121-69/+54
| | | | llvm-svn: 68887
* Add new TargetInstrDesc::hasImplicitUseOfPhysReg andChris Lattner2009-04-121-15/+3
| | | | | | | hasImplicitDefOfPhysReg methods. Use them to remove a look in X86 fast isel. llvm-svn: 68886
* Revert r68847. It breaks the build on non-Darwin targets, with this messageDan Gohman2009-04-112-2/+0
| | | | | | | from the assembler: Error: unknown pseudo-op: `.debug_inlined' llvm-svn: 68863
* Keep track of inlined functions and their locations. This information is ↵Devang Patel2009-04-112-0/+2
| | | | | | | | collected when nested llvm.dbg.func.start intrinsics are seen. (Right now, inliner removes nested llvm.dbg.func.start intrinisics during inlining.) Create debug_inlined dwarf section using these information. This info is used by gdb, at least on Darwin, to enable better experience debugging inlined functions. See DwarfWriter.cpp for more information on structure of debug_inlined section. llvm-svn: 68847
* Added code to handle spilling and reloading of FSRs.Sanjiv Gupta2009-04-104-14/+61
| | | | llvm-svn: 68783
* Don't fold a load if the other operand is a TLS address.Rafael Espindola2009-04-101-6/+27
| | | | | | | | | | | | | | With this we generate movl %gs:0, %eax leal i@NTPOFF(%eax), %eax instead of movl $i@NTPOFF, %eax addl %gs:0, %eax llvm-svn: 68778
* a few fixes to "addrspace(256) is reference offset of GS segment register".Chris Lattner2009-04-101-17/+60
| | | | | | It turns out that there are still several problems with this, will file a bugzilla. llvm-svn: 68749
* Pass in the std::string parameter instead of returning it by value.Bill Wendling2009-04-101-1/+2
| | | | llvm-svn: 68747
* Remove the obsolete SelectionDAG::getNodeValueTypes and simplifyDan Gohman2009-04-092-10/+9
| | | | | | code that uses it by using SelectionDAG::getVTList instead. llvm-svn: 68744
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