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* [WebAssembly] Remove the output operand from stores.Dan Gohman2016-10-067-88/+64
| | | | | | | | | Per spec changes, store instructions in WebAssembly no longer have a return value. Update the instruction descriptions. Differential Revision: https://reviews.llvm.org/D25122 llvm-svn: 283501
* [X86] Preserve BasePtr for LEA64_32rMichael Kuperstein2016-10-061-3/+5
| | | | | | | | | | | | When replacing FrameIndex with BasePtr, we must preserve BasePtr for LEA64_32r since BasePtr is used later for stack adjustment if it is the same as StackPtr. Patch by H.J Lu <hjl.tools@gmail.com> Differential Revision: https://reviews.llvm.org/D23575 llvm-svn: 283486
* AMDGPU: Don't fold undef uses or copies with implicit usesMatt Arsenault2016-10-061-4/+22
| | | | llvm-svn: 283476
* AMDGPU: Remove scheduling info from si_mask_branchMatt Arsenault2016-10-061-0/+2
| | | | llvm-svn: 283475
* AMDGPU: Remove leftover implicit operands when folding immediatesMatt Arsenault2016-10-061-7/+26
| | | | | | | | When constant folding an operation to a copy or an immediate mov, the implicit uses/defs of the old instruction were left behind, e.g. replacing v_or_b32 left the implicit exec use on the new copy. llvm-svn: 283471
* Reapply "AMDGPU: Support using tablegened MC pseudo expansions"Matt Arsenault2016-10-065-44/+75
| | | | | | Fix bad merge llvm-svn: 283470
* Revert "AMDGPU: Support using tablegened MC pseudo expansions"Matt Arsenault2016-10-065-68/+44
| | | | llvm-svn: 283469
* AMDGPU: Support using tablegened MC pseudo expansionsMatt Arsenault2016-10-065-44/+68
| | | | | | Make the necessary refactorings to make use of PseudoInstExpansion llvm-svn: 283467
* BranchRelaxation: Support expanding unconditional branchesMatt Arsenault2016-10-069-17/+271
| | | | | | | AMDGPU needs to expand unconditional branches in a new block with an indirect branch. llvm-svn: 283464
* [Hexagon] Avoid replacing full regs with subregisters in tied operandsKrzysztof Parzyszek2016-10-061-0/+20
| | | | | | Doing so will result in the two-address pass generating incorrect code. llvm-svn: 283463
* Move AArch64BranchRelaxation to generic codeMatt Arsenault2016-10-064-421/+2
| | | | llvm-svn: 283459
* AArch64: Move remaining target specific BranchRelaxation bits to TIIMatt Arsenault2016-10-063-53/+37
| | | | llvm-svn: 283458
* [X86] Fix intel syntax push parsing bugNirav Dave2016-10-061-2/+29
| | | | | | | | | | | | | | | Change erroneous parsing of push immediate instructions in intel syntax to default to pointer size by rewriting into the ATT style for matching. This fixes PR22028. Reviewers: majnemer, rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25288 llvm-svn: 283457
* [AMDGPU] Disassembler: print label names in branch instructionsSam Kolton2016-10-063-66/+156
| | | | | | | | | | | | | Summary: Add AMDGPUSymbolizer for finding names for labels from ELF symbol table. Initialize MCObjectFileInfo with some default values. Reviewers: vpykhtin, artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D24802 llvm-svn: 283450
* [RDF] Replace some expensive copies with references in range-based loopsKrzysztof Parzyszek2016-10-061-7/+7
| | | | llvm-svn: 283446
* [RDF] Replace potentially unclear autos with real typesKrzysztof Parzyszek2016-10-062-59/+53
| | | | llvm-svn: 283445
* Revert "[ARM] Use __rt_div functions for divrem on Windows"Diana Picus2016-10-061-45/+21
| | | | | | | | | | This reverts commit r283383 because it broke some of the bots: undefined reference to ` __aeabi_uldivmod' It affected (at least) clang-cmake-armv7-a15-selfhost, clang-cmake-armv7-a15-selfhost and clang-native-arm-lnt. llvm-svn: 283442
* AMDGPU: Partially fix reported code size for some instructionsMatt Arsenault2016-10-064-4/+8
| | | | | | | | These ones need to have the size on the pseudo instruction set for getInstSizeInBytes to work correctly. These also have a statically known size. llvm-svn: 283437
* [ARM] Constant pool promotion - fix alignment calculationJames Molloy2016-10-061-1/+1
| | | | | | | | | Global variables are GlobalValues, so they have explicit alignment. Querying DataLayout for the alignment was incorrect. Testcase added. llvm-svn: 283423
* [Triple] Add triple for FuchsiaPetr Hosek2016-10-063-0/+14
| | | | | | | | Fuchsia is a new operating system. Differential Revision: https://reviews.llvm.org/D25116 llvm-svn: 283419
* [AMDGPU] Promote uniform i16 bitreverse intrinsic to i32Konstantin Zhuravlyov2016-10-061-11/+65
| | | | | | Differential Revision: https://reviews.llvm.org/D25121 llvm-svn: 283415
* Modify df_iterator to support post-order actionsDavid Callahan2016-10-051-1/+1
| | | | | | | | | | | | Summary: This makes a change to the state used to maintain visited information for depth first iterator. We know assume a method "completed(...)" which is called after all children of a node have been visited. In all existing cases, this method does nothing so this patch has no functional changes. It will however allow a client to distinguish back from cross edges in a DFS tree. Reviewers: nadav, mehdi_amini, dberlin Subscribers: MatzeB, mzolotukhin, twoh, freik, llvm-commits Differential Revision: https://reviews.llvm.org/D25191 llvm-svn: 283391
* [WebAssembly] Add binary-encoding opcode values to instruction descriptions.Dan Gohman2016-10-058-133/+147
| | | | llvm-svn: 283389
* [ARM] Use __rt_div functions for divrem on WindowsMartin Storsjo2016-10-051-21/+45
| | | | | | | | | | | | | | | | | | | | This avoids falling back to calling out to the GCC rem functions (__moddi3, __umoddi3) when targeting Windows. The __rt_div functions have flipped the two arguments compared to the __aeabi_divmod functions. To match MSVC, we emit a check for division by zero before actually calling the library function (even if the library function itself also might do the same check). Not all calls to __rt_div functions for division are currently merged with calls to the same function with the same parameters for the remainder. This is more wasteful than a div + mls as before, but avoids calls to __moddi3. Differential Revision: https://reviews.llvm.org/D24076 llvm-svn: 283383
* [Sparc] Implement UMUL_LOHI and SMUL_LOHI instead of MULHS/MULHU/MUL.James Y Knight2016-10-053-18/+6
| | | | | | | This is what the instruction-set actually provides, and the default expansions of the others into the lohi opcodes are good. llvm-svn: 283381
* [RDF] Fix live def propagation through basic blockKrzysztof Parzyszek2016-10-051-45/+60
| | | | llvm-svn: 283371
* AMDGPU: Do not re-use tmpreg in spill/restore loweringMatthias Braun2016-10-051-2/+2
| | | | | | | | | The register scavenging code does not support multiple definitions of the same vreg. Differential Revision: https://reviews.llvm.org/D25220 llvm-svn: 283369
* [mips][ias] fix li macro when values are negated with ~Simon Dardis2016-10-052-6/+34
| | | | | | | | | | | | | | | The integrated assembler evaluates the expressions such as ~0x80000000 to 0xffffffff7fffffff early in the parsing process. This patch adds compatibility with gas so that li loads the expected value (0x7fffffff) in those cases. This only occurs iff all the upper 32bits are set and maintains existing checks by not truncating the result down to 32 bits if any of the the upper bits are not set. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23399 llvm-svn: 283353
* Recommit: "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-057-19/+43
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
* Revert r282920 "X86: Allow conditional tail calls in Win64 "leaf" functions ↵Hans Wennborg2016-10-052-6/+6
| | | | | | | | | (PR26302)" This is suspected to cause a miscompile in Chromium. Reverting while investigating. llvm-svn: 283329
* Revert "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-058-77/+25
| | | | | | | This reverts commit r282485 which contain two patches instead of one. llvm-svn: 283327
* [X86] Don't randomly encode %rip where illegalDouglas Katzman2016-10-052-4/+27
| | | | | | Differential Revision: https://reviews.llvm.org/D25112 llvm-svn: 283326
* [Thumb] Don't try and emit LDRH/LDRB from the constant poolJames Molloy2016-10-051-0/+1
| | | | | | | | This is not a valid encoding - these instructions cannot do PC-relative addressing. The underlying problem here is of whitelist in ARMISelDAGToDAG that unwraps ARMISD::Wrappers during addressing-mode selection. This didn't realise TargetConstantPool was actually possible, so didn't handle it. llvm-svn: 283323
* Test commit permissionOren Ben Simhon2016-10-051-2/+2
| | | | llvm-svn: 283318
* [AVR] Don't select 'MOVW' instructions when they are not supportedDylan McKay2016-10-051-15/+41
| | | | | | | We have a subtarget feature which we were ignoring, which was causing us to generate unsupported instructions for some older chips. llvm-svn: 283317
* [AVR] Add AVRRegisterInfo::splitReg functionDylan McKay2016-10-052-2/+14
| | | | | | | No tests are included just yet - this is used from the pseudo instruction expander pass, which hasn't been pulled in-tree yet. llvm-svn: 283316
* [AVR] Update return type of dynamic alloca passDylan McKay2016-10-051-2/+2
| | | | | | It was recently changed from 'const char*' to StringRef llvm-svn: 283312
* [AVR] Add the AVR frame lowering codeDylan McKay2016-10-052-0/+538
| | | | | | | | | | | | Summary: This allows AVR to lower frames into assembly code. Reviewers: arsenm, kparzysz Subscribers: japaric, wdng, beanz, mgorny Differential Revision: https://reviews.llvm.org/D25032 llvm-svn: 283311
* [AVR] Split all of the AVR device definitions into a separate fileDylan McKay2016-10-052-487/+493
| | | | | | | We have ~500 lines of subtarget feature definitions, they don't belong in our main TableGen file. llvm-svn: 283310
* [AVR] Enable the instruction printer in the target definitionDylan McKay2016-10-051-5/+5
| | | | llvm-svn: 283309
* [AVR] Add definitions for the ATTiny102 and ATtiny104 chipsDylan McKay2016-10-051-0/+2
| | | | llvm-svn: 283308
* [AVR] Add the machine code backendDylan McKay2016-10-053-0/+552
| | | | | | | | | | | | | | Summary: This adds the AVR machine code backend (`AVRAsmBackend.cpp`). This will allow us to generate machine code from assembled AVR instructions. Reviewers: arsenm, kparzysz Subscribers: modocache, japaric, wdng, beanz, mgorny Differential Revision: https://reviews.llvm.org/D25029 llvm-svn: 283297
* Use StringRef in ARMConstantPool APIs (NFC)Mehdi Amini2016-10-053-16/+15
| | | | llvm-svn: 283293
* [Target] move reciprocal estimate settings from TargetOptions to TargetLoweringSanjay Patel2016-10-045-65/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | The motivation for the change is that we can't have pseudo-global settings for codegen living in TargetOptions because that doesn't work with LTO. Ideally, these reciprocal attributes will be moved to the instruction-level via FMF, metadata, or something else. But making them function attributes is at least an improvement over the current state. The ingredients of this patch are: Remove the reciprocal estimate command-line debug option. Add TargetRecip to TargetLowering. Remove TargetRecip from TargetOptions. Clean up the TargetRecip implementation to work with this new scheme. Set the default reciprocal settings in TargetLoweringBase (everything is off). Update the PowerPC defaults, users, and tests. Update the x86 defaults, users, and tests. Note that if this patch needs to be reverted, the related clang patch checked in at r283251 should be reverted too. Differential Revision: https://reviews.llvm.org/D24816 llvm-svn: 283252
* AArch64: Macrofusion: Split features, add missing combinations.Matthias Braun2016-10-043-11/+59
| | | | | | | | | | | | | | | | AArch64InstrInfo::shouldScheduleAdjacent() determines whether two instruction can benefit from macroop fusion on apple CPUs. The list turned out to be incomplete: - the "rr" variants of the instructions were missing - even the "rs" variants can have shift value == 0 and behave like the "rr" variants This also splits the MacropFusion target feature into ArithmeticBccFusion and ArithmeticCbzFusion. Differential Revision: https://reviews.llvm.org/D25142 llvm-svn: 283243
* [Power9] Exploit D-Form VSX Scalar memory ops that target full VSX register setNemanja Ivanovic2016-10-043-6/+81
| | | | | | | | | | | | | This patch corresponds to review: The newly added VSX D-Form (register + offset) memory ops target the upper half of the VSX register set. The existing ones target the lower half. In order to unify these and have the ability to target all the VSX registers using D-Form operations, this patch defines Pseudo-ops for the loads/stores which are expanded post-RA. The expansion then choses the correct opcode based on the register that was allocated for the operation. llvm-svn: 283212
* [mips][fastisel] Consider soft-float an unsupported floating point modeSimon Dardis2016-10-041-2/+6
| | | | | | | | | | | Treat soft-float as unsupported for fast-isel. Additionally, ensure we check that lowering f32 arguments also considers the case of soft-float mode. Reviewers: ehostunreach, vkalintiris, zoran.jovanovic Differential Review: https://reviews.llvm.org/D24505 llvm-svn: 283209
* Consistent fp denormal mode names. NFC.Sjoerd Meijer2016-10-042-5/+5
| | | | | | | | | This fixes the inconsistency of the fp denormal option names: in LLVM this was DenormalType, but in Clang this is DenormalMode which seems better. Differential Revision: https://reviews.llvm.org/D24906 llvm-svn: 283192
* [Power9] Part-word VSX integer scalar loads/stores and sign extend instructionsNemanja Ivanovic2016-10-0418-157/+582
| | | | | | | | | | | | | | | | | | This patch corresponds to review: https://reviews.llvm.org/D23155 This patch removes the VSHRC register class (based on D20310) and adds exploitation of the Power9 sub-word integer loads into VSX registers as well as vector sign extensions. The new instructions are useful for a few purposes: Int to Fp conversions of 1 or 2-byte values loaded from memory Building vectors of 1 or 2-byte integers with values loaded from memory Storing individual 1 or 2-byte elements from integer vectors This patch implements all of those uses. llvm-svn: 283190
* [X86] Add MOV8rm_NOREX to switch in isReallyTriviallyReMaterializable to ↵Craig Topper2016-10-041-0/+1
| | | | | | match MOV8rm. llvm-svn: 283184
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