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* Be careful not to walk off the end of the operand info list while updating ↵Owen Anderson2011-08-241-1/+2
| | | | | | VFP predicates. llvm-svn: 138492
* Thumb parsing and encoding support for ADD SP instructions.Jim Grosbach2011-08-242-17/+77
| | | | | | | Fix the test FIXME and add parsing support for the ADD (SP plus immediate) and ADD (SP plus register) instruction forms. llvm-svn: 138488
* Fix whitespace.Eli Friedman2011-08-241-8/+8
| | | | llvm-svn: 138487
* Basic x86 code generation for atomic load and store instructions.Eli Friedman2011-08-242-0/+36
| | | | llvm-svn: 138478
* When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.Jim Grosbach2011-08-241-0/+1
| | | | | | rdar://10015134 llvm-svn: 138467
* Mark VZEROALL as clobbering all YMM registersBruno Cardoso Lopes2011-08-241-3/+7
| | | | llvm-svn: 138461
* Add missing explicit writeback operand to tSTMIA_UPD.Jim Grosbach2011-08-242-4/+5
| | | | | | rdar://10014745 llvm-svn: 138457
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-2492-219/+90
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Thumb add SP assembly syntax fix.Jim Grosbach2011-08-241-2/+2
| | | | llvm-svn: 138448
* Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.Jim Grosbach2011-08-248-39/+39
| | | | | | | | | Add the predicate operand to the instructions. Update the back end accordingly where the instructions are used. Restrict the SP operands to actually only be SP, as otherwise these break assembly parsing for the normal instruction variants. llvm-svn: 138445
* Be stricter in enforcing IT instruction predicate values, so that we don't ↵Owen Anderson2011-08-242-0/+15
| | | | | | end up trying to print out an illegal predicate. llvm-svn: 138443
* Add Uses=[SP] to call instructions. This fixes a miscompilation with aRichard Osborne2011-08-241-2/+2
| | | | | | variable sized alloca. llvm-svn: 138433
* Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid ↵Craig Topper2011-08-242-3/+72
| | | | | | costly scalarization. Fixes PR10711. llvm-svn: 138427
* Fix a nasty bug where a v4i64 was being wrong emitted with 32-bitBruno Cardoso Lopes2011-08-232-55/+106
| | | | | | | permutations. Also tidy up some patterns and make them close to their instruction definition! llvm-svn: 138392
* Move ARM frame-unwinding EHABI handling a touch earlier.Jim Grosbach2011-08-231-4/+4
| | | | | | | | It should go before AsmPrinter MC pseudo expansion since it's based on MachineInstr, not MCInst. Otherwise any frame related pseudo instructions may be missed. llvm-svn: 138386
* [SU]XT[BH] are only available on ARMv6 and up.Jim Grosbach2011-08-231-0/+2
| | | | llvm-svn: 138373
* Some refactoring so TargetRegistry.h no longer has to include any filesEvan Cheng2011-08-2314-5/+32
| | | | | | from MC. llvm-svn: 138367
* Thumb parsing and encoding for SVC.Jim Grosbach2011-08-231-1/+1
| | | | llvm-svn: 138360
* PerformSubCombine to work on integers larger than i128. Fixes a crasher.Nick Lewycky2011-08-231-4/+2
| | | | llvm-svn: 138354
* Thumb parsing and encoding for tSTRspi.Jim Grosbach2011-08-231-0/+2
| | | | llvm-svn: 138348
* Thumb parsing and encoding for STM.Jim Grosbach2011-08-231-0/+7
| | | | llvm-svn: 138345
* Factor low reg checking into a helper function.Jim Grosbach2011-08-231-26/+32
| | | | llvm-svn: 138344
* Fix decoding of Thumb2 prefetch instructions, which account for all the ↵Owen Anderson2011-08-231-3/+9
| | | | | | remaining Thumb2 decoding failures found by randomized testing so far. llvm-svn: 138341
* Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same ↵Owen Anderson2011-08-233-10/+44
| | | | | | instructions. llvm-svn: 138339
* Clean up Thumb load/store multiple definitions.Jim Grosbach2011-08-233-45/+36
| | | | | | | | There is no non-writeback store multiple instruction in Thumb1, so don't define one. As a result load multiple is the only instantiation of the multiclass, so refactor that away entirely. llvm-svn: 138338
* Fix two more instances of mis-matched operand names breaking disassembly. ↵Owen Anderson2011-08-231-6/+6
| | | | | | Found by randomized testing. llvm-svn: 138337
* Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ↵Craig Topper2011-08-232-1/+20
| | | | | | ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712. llvm-svn: 138321
* Introduce a pass to insert vzeroupper instructions to avoid AVX toBruno Cardoso Lopes2011-08-234-0/+127
| | | | | | | | | | SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper" llc command line option. This is only the first step (very naive and conservative one) to sketch out the idea, but proper DFA is coming next to allow smarter decisions. Comments and ideas now and in further commits will be very appreciated. llvm-svn: 138317
* Thumb parsing and encoding for SBC.Jim Grosbach2011-08-221-1/+2
| | | | llvm-svn: 138311
* Thumb parsing and encoding for RSB.Jim Grosbach2011-08-221-0/+13
| | | | llvm-svn: 138308
* Reject invalid imod values in t2CPS instructions.Owen Anderson2011-08-222-1/+11
| | | | llvm-svn: 138306
* t2SMLAD is a four-register instruction, not a three-register one.Owen Anderson2011-08-221-1/+1
| | | | llvm-svn: 138301
* Correct operand naming of t2USAT16 to allow proper decoding.Owen Anderson2011-08-221-2/+2
| | | | llvm-svn: 138300
* Revert r138278 now that r138289 has fixed the root issue.Jim Grosbach2011-08-221-1/+1
| | | | llvm-svn: 138299
* Match operand naming to allow correct decoding of t2LDRSH_POST.Owen Anderson2011-08-221-2/+2
| | | | llvm-svn: 138298
* Improve error checking for tPUSH and tPOP register lists.Jim Grosbach2011-08-221-0/+20
| | | | llvm-svn: 138295
* Match operand names to provide correct decoding for Thumb2 SMULL.Owen Anderson2011-08-221-2/+2
| | | | llvm-svn: 138294
* Provide a correct decoder hook for Thumb2 shifted registers. Found by ↵Owen Anderson2011-08-221-0/+1
| | | | | | randomized testing. llvm-svn: 138292
* Thumb assemmbly parsing diagnostic improvements for LDM.Jim Grosbach2011-08-221-4/+10
| | | | llvm-svn: 138287
* X86: Add some operand types required to identify calls.Benjamin Kramer2011-08-221-0/+2
| | | | llvm-svn: 138285
* Temporarilly mark tMUL as not commutable.Jim Grosbach2011-08-221-1/+1
| | | | | | | It's not playing nicely in the coalescer with the tied operand. Disable commutability for now while we figure out the deeper fix. llvm-svn: 138278
* Provide operand encoding information for half-precision VCVT instructions. ↵Owen Anderson2011-08-221-8/+8
| | | | | | Found by randomized testing. llvm-svn: 138273
* Add support for breaking 256-bit int VETCC into two 128-bit ones,Bruno Cardoso Lopes2011-08-221-1/+35
| | | | | | | avoding scalarization of the compare. Reduces code from 59 to 6 instructions. Fix PR10712. llvm-svn: 138271
* Add 128-bit AVX codegen for PCMP* family of integer instructionsBruno Cardoso Lopes2011-08-221-0/+26
| | | | llvm-svn: 138270
* Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming ↵Owen Anderson2011-08-222-0/+48
| | | | | | majority of decoder crashes detected by randomized testing. llvm-svn: 138269
* Tighten up ARM reglist validation a bit.Jim Grosbach2011-08-221-11/+6
| | | | llvm-svn: 138258
* Fix another batch of VLD/VST decoding crashes discovered by randomized testing.Owen Anderson2011-08-221-16/+40
| | | | llvm-svn: 138255
* Correct writeback handling of duplicating VLD instructions. Discovered by ↵Owen Anderson2011-08-221-4/+4
| | | | | | randomized testing. llvm-svn: 138251
* Clean up predicates on ARM target instruction aliases.Jim Grosbach2011-08-224-61/+61
| | | | llvm-svn: 138249
* Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add ↵Owen Anderson2011-08-221-1/+1
| | | | | | more tests. llvm-svn: 138246
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