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* Allow sret on the second parameter as well as the firstReid Kleckner2014-05-093-30/+34
| | | | | | | | | | | | | | | | | | | | | | | | | MSVC always places the implicit sret parameter after the implicit this parameter of instance methods. We used to handle this for x86_thiscallcc by allocating the sret parameter on the stack and leaving the this pointer in ecx, but that doesn't handle alternative calling conventions like cdecl, stdcall, fastcall, or the win64 convention. Instead, change the verifier to allow sret on the second parameter. This also requires changing the Mips and X86 backends to return the argument with the sret parameter, instead of assuming that the sret parameter comes first. The Sparc backend also returns sret parameters in a register, but I wasn't able to update it to handle secondary sret parameters. It currently calls report_fatal_error if you feed it an sret in the second parameter. Reviewers: rafael.espindola, majnemer Differential Revision: http://reviews.llvm.org/D3617 llvm-svn: 208453
* Fix broken buildJonathan Roelofs2014-05-091-1/+1
| | | | | | ARM64 backend was missing a required_library entry. llvm-svn: 208437
* Add custom lowering for add/sub with overflow intrinsics to ARMLouis Gerbarg2014-05-092-0/+97
| | | | | | | | | | | | | This patch adds support to ARM for custom lowering of the llvm.{u|s}add.with.overflow.i32 intrinsics for i32/i64. This is particularly useful for handling idiomatic saturating math functions as generated by InstCombineCompare. Test cases included. rdar://14853450 llvm-svn: 208435
* R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructionsTom Stellard2014-05-091-4/+35
| | | | llvm-svn: 208432
* R600/SI: Fix SMRD pattern for offsets > 32 bitsTom Stellard2014-05-092-7/+6
| | | | | | We were dropping the high bits of 64-bit immediate offsets. llvm-svn: 208431
* R600: Expand i64 SELECT_CCTom Stellard2014-05-091-0/+2
| | | | llvm-svn: 208430
* R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()Tom Stellard2014-05-094-23/+19
| | | | llvm-svn: 208429
* [mips] Marked up instructions added in MIPS-IV and tested that IAS for ↵Daniel Sanders2014-05-095-24/+41
| | | | | | | | | | | | | | | | | | | | | -mcpu=mips[123] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-IV that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. Depends on D3676 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3677 llvm-svn: 208414
* ARM: HFAs must be passed in consecutive registersOliver Stannard2014-05-094-25/+217
| | | | | | | | | | When using the ARM AAPCS, HFAs (Homogeneous Floating-point Aggregates) must be passed in a block of consecutive floating-point registers, or on the stack. This means that unused floating-point registers cannot be back-filled with part of an HFA, however this can currently happen. This patch, along with the corresponding clang patch (http://reviews.llvm.org/D3083) prevents this. llvm-svn: 208413
* [mips] Remove unused CondMov feature bitDaniel Sanders2014-05-094-15/+7
| | | | | | | | | | | | | | | Summary: No functional change Depends on D3675 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3676 llvm-svn: 208410
* [mips] Marked up instructions added in MIPS-III and tested that IAS for ↵Daniel Sanders2014-05-096-61/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
* Fix 80 col violation.Andrea Di Biagio2014-05-091-1/+2
| | | | | | No functional change intended. llvm-svn: 208405
* [asan] Stop leaking X86Operands.Benjamin Kramer2014-05-091-4/+4
| | | | llvm-svn: 208400
* [mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6Daniel Sanders2014-05-096-2/+189
| | | | | | | | | | | | | | | | | | Summary: Adds MIPS32r6/MIPS64r6 and checks the compatibility requirements for these processors. I've also included comments to describe removed and re-encoded instructions, along with placeholder def's for the new instructions but there are no functional changes to codegen at this point. Reviewers: jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3622 llvm-svn: 208399
* [mips] Added missing dsra -> dsrav and sra -> srav aliases.Daniel Sanders2014-05-092-2/+6
| | | | | | | | | | | | Summary: dsll, dsrl, sll, and srl already exist. Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3673 llvm-svn: 208397
* ARM: support PIC on Windows on ARMSaleem Abdulrasool2014-05-092-2/+27
| | | | | | | | Handle lowering of global addresses for PIC mode compilation on Windows. Always use the movw/movt load to load the address as Windows on ARM requires ARMv7+ and is a pure Thumb environment. llvm-svn: 208385
* Optimize shufflevector that copies an i64/f64 and zeros the rest.Filipe Cabecinhas2014-05-081-12/+12
| | | | | | | | | | | | | | Summary: Also ran clang-format on the function. The code added is the last else if block. Reviewers: nadav, craig.topper, delena Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3518 llvm-svn: 208372
* [Hexagon] Add new InstrItinClass to support timing classes.Jyotsna Verma2014-05-085-138/+216
| | | | | | | This patch doesn't introduce any functionality change. Test cases will be added later when v5 support is added. llvm-svn: 208349
* Use for range loops.Rafael Espindola2014-05-081-13/+9
| | | | llvm-svn: 208348
* R600: Promote f64 vector load/stores to i64 for consistencyMatt Arsenault2014-05-081-0/+6
| | | | llvm-svn: 208344
* [X86] Add target specific combine rules to fold SSE2/AVX2 packed arithmetic ↵Andrea Di Biagio2014-05-081-0/+55
| | | | | | | | | | | | | | | | | | | | shift intrinsics. This patch teaches the backend how to combine packed SSE2/AVX2 arithmetic shift intrinsics. The rules are: - Always fold a packed arithmetic shift by zero to its first operand; - Convert a packed arithmetic shift intrinsic dag node into a ISD::SRA only if the shift count is known to be smaller than the vector element size. This patch also teaches to function 'getTargetVShiftByConstNode' how fold target specific vector shifts by zero. Added two new tests to verify that the DAGCombiner is able to fold sequences of SSE2/AVX2 packed arithmetic shift calls. llvm-svn: 208342
* [mips] Add PredicateControl to InstAlias'sDaniel Sanders2014-05-084-107/+115
| | | | | | | | | | | | | | | Summary: No functional change Depends on D3649 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3672 llvm-svn: 208334
* [ARM64] Add diagnostics for expected arithmetic shiftsBradley Smith2014-05-083-14/+32
| | | | llvm-svn: 208330
* [ARM64] Re-work parsing of ADD/SUB shifted immediate operandsBradley Smith2014-05-083-130/+210
| | | | | | | | | | | | The parsing of ADD/SUB shifted immediates needs to be done explicitly so that better diagnostics can be emitted, as a side effect this also removes some of the hacks in the current method of handling this operand type. Additionally remove manual CMP aliasing to ADD/SUB and use InstAlias instead. llvm-svn: 208329
* [ARM64] Ensure immediates in extend operands are in a valid rangeBradley Smith2014-05-082-4/+19
| | | | | | Also emit a more useful diagnostic when they are not. llvm-svn: 208318
* [ARM64] Check for proper immediate in shift/extend operandsBradley Smith2014-05-081-42/+58
| | | | llvm-svn: 208317
* ARM big endian function argument passingChristian Pirker2014-05-081-11/+30
| | | | llvm-svn: 208316
* [mips] Implement l[wd]c3, and s[wd]c3.Daniel Sanders2014-05-083-2/+45
| | | | | | | | | | | | | | | | | | | | | Summary: These instructions were added in MIPS-I, and MIPS-II but were removed in MIPS-III. Interestingly, GAS continues to accept them when assembling for MIPS-III. For the moment, these instructions will follow GAS and accept them for MIPS-III and newer but this will be tightened up when the invalid-*.s tests are added. Depends on D3647 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3648 llvm-svn: 208311
* [ARM64-BE] Teach fast-isel about how to set up sub-word stack arguments for ↵James Molloy2014-05-081-1/+7
| | | | | | | | big endian calls. SelectionDAG already knows about this, but fast-isel was ignorant. llvm-svn: 208307
* [mips] Marked up instructions added in MIPS-II and tested that IAS for ↵Daniel Sanders2014-05-083-24/+31
| | | | | | | | | | | | | | | | | | | -mcpu=mips1 does not accept them Summary: A small number of instructions are rejected with the wrong error message. These have been placed in a separate test for now. There seems to be some parsing quirk that triggers when these instructions are disabled. Depends on D3571 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3647 llvm-svn: 208305
* [mips] Implement tlbp, tlbr, tlbwi, and tlbwrDaniel Sanders2014-05-082-0/+16
| | | | | | | | | | Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3571 llvm-svn: 208301
* ARM64: make sure FastISel emits SSA MachineInstrsTim Northover2014-05-081-3/+4
| | | | | | We need to use a temporary register for a 2-step operation like REM. llvm-svn: 208297
* [asan] Preserve flags in asm instrumentation.Evgeniy Stepanov2014-05-081-8/+32
| | | | | | Patch by Yuri Gorshenin. llvm-svn: 208296
* Move late partial-unrolling thresholds into the processor definitionsHal Finkel2014-05-085-76/+13
| | | | | | | | | | | | | | | | | | | | | | The old method used by X86TTI to determine partial-unrolling thresholds was messy (because it worked by testing target features), and also would not correctly identify the target CPU if certain target features were disabled. After some discussions on IRC with Chandler et al., it was decided that the processor scheduling models were the right containers for this information (because it is often tied to special uop dispatch-buffer sizes). This does represent a small functionality change: - For generic x86-64 (which uses the SB model and, thus, will get some unrolling). - For AMD cores (because they still currently use the SB scheduling model) - For Haswell (based on benchmarking by Louis Gerbarg, it was decided to bump the default threshold to 50; we're working on a test case for this). Otherwise, nothing has changed for any other targets. The logic, however, has been moved into BasicTTI, so other targets may now also opt-in to this functionality simply by setting LoopMicroOpBufferSize in their processor model definitions. llvm-svn: 208289
* AArch64/ARM64: Port NEON post-increment load/store with 2/3/4 vectors to ↵Hao Liu2014-05-083-56/+743
| | | | | | ARM64 backend. llvm-svn: 208284
* ARM: support FK_SecRel_2 relocations on WoASaleem Abdulrasool2014-05-082-0/+6
| | | | | | | | This adds FK_SecRel_2 relocation support to ARM. This enables the building of object files for armv7-windows-msvc which enables CodeView line tables for debugging as opposed to armv7-windows-itanium which currently uses DWARF. llvm-svn: 208273
* Lower certain build_vectors to insertps instructionsFilipe Cabecinhas2014-05-081-0/+76
| | | | | | | | | | | | | | | | | | | | | | Summary: Vectors built with zeros and elements in the same order as another (source) vector are optimized to be built using a single insertps instruction. Also optimize when we move one element in a vector to a different place in that vector while zeroing out some of the other elements. Further optimizations are possible, described in TODO comments. I will be implementing at least some of them in the near future. Added some tests for different cases where this optimization triggers. Reviewers: nadav, delena, craig.topper Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3521 llvm-svn: 208271
* [X86TTI] Remove the unrolling branch limitsHal Finkel2014-05-071-40/+13
| | | | | | | | | | | | | | | | | | | | The loop stream detector (LSD) on modern Intel cores, which optimizes the execution of small loops, has limits on the number of taken branches in addition to uop-count limits (modern AMD cores have similar limits). Unfortunately, at the IR level, estimating the number of branches that will be taken is difficult. For one thing, it strongly depends on later passes (block placement, etc.). The original implementation took a conservative approach and limited the maximal BB DFS depth of the loop. However, fairly-extensive benchmarking by several of us has revealed that this is the wrong approach. In fact, there are zero known cases where the branch limit prevents a detrimental unrolling (but plenty of cases where it does prevent beneficial unrolling). While we could improve the current branch counting logic by incorporating branch probabilities, this further complication seems unjustified without a motivating regression. Instead, unless and until a regression appears, the branch counting will be removed. llvm-svn: 208255
* [X86] Selectively mark the FMA variants inside a family as isCommutable.Quentin Colombet2014-05-071-14/+32
| | | | | | | | | | | | | | | | | | | Given a FMA family (e.g., 213, 231), not all the variants (i.e., register or memory) are commutable. E.g., for the 213 family (with the syntax src1, src2, src3): fmaXXX213 A, B, reg3/mem3 == fmaXXX213 B, A, reg3/mem3 Now consider the 231 family: fmaXXX231 A, B, reg3 == fmaXXX231 A, reg3, B But fmaXXX231 A, B, mem3 != fmaXXX231 A, mem3, B Indeed, mem3 cannot be the second argument of the memory variant of fmaXXX231. Working on a reduced test case! <rdar://problem/16800495> llvm-svn: 208252
* Reformat a couple of functions for clarity.Eric Christopher2014-05-071-22/+19
| | | | llvm-svn: 208248
* [Hexagon] Add New TSFlags to be used in the upcoming patches.Jyotsna Verma2014-05-074-67/+102
| | | | llvm-svn: 208239
* [x86] Make the 'x86-64' cpu, what I see as and many use as the genericChandler Carruth2014-05-071-2/+15
| | | | | | | | | | | | | | | | default architecture for reasonable modern x86 processors, actually be modern. This processor model should essentially be "tuned" for modern x86 chips as much as possible without undue penalties on any specific architecture. Previously we weren't even using the nice scheduling models. There are a few other tweaks needed here, but this change at least I have benchmarked across a decent swatch of chips (intel's clovertown, westmere, and sandybridge; amd's istanbul) and seen no significant regressions. If anyone has suggested ways to test this, just let me know. Somewhat alarmingly, no existing tests failed. llvm-svn: 208230
* [ARM64][fast-isel] Disable target specific optimizations at -O0. Functionally,Chad Rosier2014-05-073-31/+30
| | | | | | | | | | | | | | | this patch disables the dead register elimination pass and the load/store pair optimization pass at -O0. The ILP optimizations don't require the optimization level to be checked because the call to addILPOpts is predicated with the necessary check. The AdvSIMDScalar pass is disabled by default at all optimization levels. This patch leaves that pass disabled by default. Also, move command-line options into ARM64TargetMachine.cpp and add a few additional flags to aid in debugging. This fixes an issue with the -debug-pass=Structure flag where passes were printed, but not actually run (i.e., AdvSIMDScalar pass). llvm-svn: 208223
* [mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-VDaniel Sanders2014-05-073-5/+38
| | | | | | | | | | | | | | | | | | | | Summary: These processors will only be available for the integrated assembler at first (CodeGen will emit a fatal error saying they are not implemented). The intention is to work through the existing instructions and correctly annotate the ISA they were added in so that we have a sufficiently good base to start MIPS64r6 development. MIPS64r6 removes/re-encodes certain instructions and I believe it is best to define ISA's using set-union's as far as possible rather than using set-subtraction. Reviewers: vmedic Subscribers: emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D3569 llvm-svn: 208221
* Use range loop.Rafael Espindola2014-05-071-3/+2
| | | | llvm-svn: 208218
* [mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of ↵Daniel Sanders2014-05-073-161/+156
| | | | | | | | | | | | | | | | | FGRPredicates/GPRPredicates Summary: No functional change (confirmed by diffing tablegen-erated files). Depends on D3642 Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3645 llvm-svn: 208213
* [mips] Add INSN_<name> adverbs and start using them instead of ↵Daniel Sanders2014-05-071-6/+8
| | | | | | | | | | | | | | | | | AdditionalPredicates overrides Summary: No functional change Depends on D3641 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3642 llvm-svn: 208212
* AArch64/ARM64: optimise vector selects & enable testTim Northover2014-05-071-0/+41
| | | | | | | | | When performing a scalar comparison that feeds into a vector select, it's actually better to do the comparison on the vector side: the scalar route would be "CMP -> CSEL -> DUP", the vector is "CM -> DUP" since the vector comparisons are all mask based. llvm-svn: 208210
* [mips] Add ISA_<name> adverbs and start using them instead of ↵Daniel Sanders2014-05-074-42/+46
| | | | | | | | | | | | | | | | | | AdditionalPredicates overrides Summary: One small functional change. The recently added PAUSE instruction now has the HasStdEnc predicate which was accidentally removed by a Requires<>. Depends on D3640 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3641 llvm-svn: 208209
* Remove the UseCFI option from createAsmStreamer.Rafael Espindola2014-05-076-23/+16
| | | | | | We were already always passing true, this just removes the option. llvm-svn: 208205
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