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* Add the IR attribute 'sspstrong'.Bill Wendling2013-01-231-0/+1
| | | | | | | | | | | | | | | | | | | | | SSPStrong applies a heuristic to insert stack protectors in these situations: * A Protector is required for functions which contain an array, regardless of type or length. * A Protector is required for functions which contain a structure/union which contains an array, regardless of type or length. Note, there is no limit to the depth of nesting. * A protector is required when the address of a local variable (i.e., stack based variable) is exposed. (E.g., such as through a local whose address is taken as part of the RHS of an assignment or a local whose address is taken as part of a function argument.) This patch implements the SSPString attribute to be equivalent to SSPRequired. This will change in a subsequent patch. llvm-svn: 173230
* R600: rework handling of the constantsTom Stellard2013-01-2316-104/+483
| | | | | | | | | | | | | | | | | | | | Remove Cxxx registers, add new special register - "ALU_CONST" and new operand for each alu src - "sel". ALU_CONST is used to designate that the new operand contains the value to override src.sel, src.kc_bank, src.chan for constants in the driver. Patch by: Vadim Girlin Vincent Lejeune: - Use pointers for constants - Fold CONST_ADDRESS when possible Tom Stellard: - Give CONSTANT_BUFFER_0 its own address space - Use integer types for constant loads Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 173222
* R600: Add a CONST_ADDRESS node to model constant buf readTom Stellard2013-01-233-1/+12
| | | | | | | Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 173221
* R600: Factorise VTX_WORD0 and VTX_WORD1 in tblgen defTom Stellard2013-01-231-45/+65
| | | | | | | Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 173220
* Add instruction encodings / disassembly support for u10 / lu10 instructions.Richard Osborne2013-01-222-12/+22
| | | | llvm-svn: 173204
* Fix an issue of pseudo atomic instruction DAG scheduleMichael Liao2013-01-222-3/+8
| | | | | | | | | | - Add list of physical registers clobbered in pseudo atomic insts Physical registers are clobbered when pseudo atomic instructions are expanded. Add them in clobber list to prevent DAG scheduler to mis-schedule them after these insns are declared side-effect free. - Add test case from Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 173200
* [mips] Implement MipsRegisterInfo::getRegPressureLimit.Akira Hatanaka2013-01-222-0/+24
| | | | llvm-svn: 173197
* [mips] Clean up code in MipsTargetLowering::LowerCall. No functional changeAkira Hatanaka2013-01-222-21/+14
| | | | | | intended llvm-svn: 173189
* X86: Make sure we account for the FMA4 register immediate value, otherwise ↵Benjamin Kramer2013-01-221-1/+1
| | | | | | | | rip-rel relocations will be off by one byte. PR15040. llvm-svn: 173176
* Initial patch for x32 ABI support.Eli Bendersky2013-01-221-3/+11
| | | | | | | | Add the x32 environment kind to the triple, and separate the concept of pointer size and callee save stack slot size, since they're not equal on x32. llvm-svn: 173175
* Make APFloat constructor require explicit semantics.Tim Northover2013-01-221-18/+30
| | | | | | | | | Previously we tried to infer it from the bit width size, with an added IsIEEE argument for the PPC/IEEE 128-bit case, which had a default value. This default value allowed bugs to creep in, where it was inappropriate. llvm-svn: 173138
* Fix some incorrectly named u10 / lu10 instructions.Richard Osborne2013-01-211-25/+12
| | | | llvm-svn: 173090
* Remove unused multiclass.Richard Osborne2013-01-211-12/+0
| | | | llvm-svn: 173087
* Add instruction encodings / disassembly support for u6 / lu6 instructions.Richard Osborne2013-01-212-59/+42
| | | | llvm-svn: 173086
* Add instruction encoding / disassembly support for ru6 / lru6 instructions.Richard Osborne2013-01-213-94/+97
| | | | llvm-svn: 173085
* Use correct format for the LDAWCP instruction (u6).Richard Osborne2013-01-211-7/+3
| | | | llvm-svn: 173083
* R600/SI: Use unnormalized coordinates for sampling with the RECT target.Tom Stellard2013-01-212-0/+13
| | | | | | | | | Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 173053
* R600/SI: Take target parameter for sample intrinsics.Tom Stellard2013-01-212-4/+4
| | | | | | | | | Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 173052
* R600/SI: Derive all sample intrinsics from a single class.Tom Stellard2013-01-211-3/+5
| | | | | | | | | Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 173051
* R600/SILowerControlFlow.cpp: Fix a warning. [-Wunused-variable]NAKAMURA Takumi2013-01-211-3/+2
| | | | llvm-svn: 173040
* Use <0 checks in place of ==-1 because it results in simpler code.Craig Topper2013-01-211-3/+3
| | | | llvm-svn: 173010
* Use MVT instead of EVT in LowerVECTOR_SHUFFLEtoBlend.Craig Topper2013-01-211-6/+5
| | | | llvm-svn: 173009
* Remove trailing whitespace.Craig Topper2013-01-211-9/+9
| | | | llvm-svn: 173008
* Fix some 80 column violations.Craig Topper2013-01-211-7/+9
| | | | llvm-svn: 173006
* Make helper method static.Craig Topper2013-01-212-4/+2
| | | | llvm-svn: 173005
* Convert more EVT's to MVT's in the lowering methods.Craig Topper2013-01-201-23/+24
| | | | llvm-svn: 172995
* Capitalize lowerTRUNCATE so that it matches the other lower functions in ↵Craig Topper2013-01-202-3/+3
| | | | | | this file despite it not matching coding standards. llvm-svn: 172994
* Revert CostTable algorithm, will re-writeRenato Golin2013-01-201-66/+102
| | | | llvm-svn: 172992
* Add instruction encodings / disassembly support for l2rus instructions.Richard Osborne2013-01-203-23/+81
| | | | llvm-svn: 172987
* Add instruction encodings / disassembly support for l3r instructions.Richard Osborne2013-01-203-56/+172
| | | | llvm-svn: 172986
* Add instruction encodings / disassembler support for 2rus instructions.Richard Osborne2013-01-203-23/+90
| | | | llvm-svn: 172985
* Add instruction encodings / disassembly support 3r instructions.Richard Osborne2013-01-203-85/+167
| | | | | | | | It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. llvm-svn: 172984
* Make LowerVSETCC a static function and use MVT instead of EVT.Craig Topper2013-01-202-63/+65
| | | | llvm-svn: 172969
* Revert 172708.Nadav Rotem2013-01-201-26/+2
| | | | | | | | | The optimization handles esoteric cases but adds a lot of complexity both to the X86 backend and to other backends. This optimization disables an important canonicalization of chains of SEXT nodes and makes SEXT and ZEXT asymmetrical. Disabling the canonicalization of consecutive SEXT nodes into a single node disables other DAG optimizations that assume that there is only one SEXT node. The AVX mask optimizations is one example. Additionally this optimization does not update the cost model. llvm-svn: 172968
* Make some helper methods static.Craig Topper2013-01-202-9/+3
| | | | llvm-svn: 172936
* Remove DebugLoc argument from static function. It can easily be obtained ↵Craig Topper2013-01-201-4/+5
| | | | | | from the SVOp passed in. llvm-svn: 172935
* Use MVT instead of EVT in more instruction lowering code.Craig Topper2013-01-201-17/+17
| | | | llvm-svn: 172933
* Use MVT instead of EVT in more of the shuffle lowering code.Craig Topper2013-01-191-15/+15
| | | | llvm-svn: 172930
* Capitalize LowerVectorIntExtend to be consistent with all the other lower ↵Craig Topper2013-01-192-3/+3
| | | | | | functions in this file. llvm-svn: 172927
* On Sandybridge split unaligned 256bit stores into two xmm-sized stores. Nadav Rotem2013-01-191-9/+18
| | | | llvm-svn: 172894
* Use MVT instead of EVT when computing shuffle immediates since they can only ↵Craig Topper2013-01-191-10/+10
| | | | | | be for legal types. Keeps compiler from generating unneeded checks and handling for extended types. llvm-svn: 172893
* Sort all of the includes. Several files got checked in with mis-sortedChandler Carruth2013-01-191-1/+1
| | | | | | includes. llvm-svn: 172891
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-196-34/+52
| | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Formatting fixes. Mostly long lines and blank spaces at end of lines. Contributer: Jack Carter llvm-svn: 172882
* On Sandybridge loading unaligned 256bits using two XMM loads (vmovups and ↵Nadav Rotem2013-01-181-1/+31
| | | | | | vinsertf128) is faster than using a single vmovups instruction. llvm-svn: 172868
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-188-1/+145
| | | | | | | | | | | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Support for Mips register information sections. Mips ELF object files have a section that is dedicated to register use info. Some of this information such as the assumed Global Pointer value is used by the linker in relocation resolution. The register info file is .reginfo in o32 and .MIPS.options in 64 and n32 abi files. This patch contains the changes needed to create the sections, but leaves the actual register accounting for a future patch. Contributer: Jack Carter llvm-svn: 172847
* R600: Proper insert S_WAITCNT instructionsTom Stellard2013-01-188-32/+379
| | | | | | | | | | | | | | | | Some instructions like memory reads/writes are executed asynchronously, so we need to insert S_WAITCNT instructions to block before accessing their results. Previously we have just inserted S_WAITCNT instructions after each async instruction, this patch fixes this and adds a prober insertion pass. Patch by: Christian König Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> llvm-svn: 172846
* R600: Optimize and cleanup KILL on SITom Stellard2013-01-184-71/+96
| | | | | | | | | | | | We shouldn't insert KILL optimization if we don't have a kill instruction at all. Patch by: Christian König Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> llvm-svn: 172845
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-182-47/+57
| | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
* Calculate vector element size more directly for VINSERTF128/VEXTRACTF128 ↵Craig Topper2013-01-181-6/+4
| | | | | | immediate handling. Also use MVT since this only called on legal types during pattern matching. llvm-svn: 172797
* Minor formatting fix. No functional change.Craig Topper2013-01-181-1/+1
| | | | llvm-svn: 172795
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