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* Added source file/line correspondence for dwarf (PowerPC only at this point.)Jim Laskey2005-12-163-0/+27
| | | | llvm-svn: 24748
* Weak and linkonce global vars should still have a .globl emitted for themChris Lattner2005-12-161-1/+2
| | | | llvm-svn: 24747
* Add a second vector type to the VRRC register class, and fix some patternsNate Begeman2005-12-162-6/+6
| | | | | | so that tablegen can infer all types. llvm-svn: 24746
* add some notesChris Lattner2005-12-161-0/+9
| | | | llvm-svn: 24745
* Add a couple more instrsChris Lattner2005-12-162-4/+8
| | | | llvm-svn: 24744
* remove some dead codeChris Lattner2005-12-161-22/+0
| | | | llvm-svn: 24743
* asmprint pseudo instrsChris Lattner2005-12-162-24/+10
| | | | llvm-svn: 24742
* Autogenerate asmprinter for F3_2 instructionsChris Lattner2005-12-163-127/+129
| | | | llvm-svn: 24741
* Switch F3_1 instructions over to use AsmStringsChris Lattner2005-12-163-111/+146
| | | | llvm-svn: 24740
* Plug in basic hooks for an autogenerated asm printer to fill in.Chris Lattner2005-12-162-14/+19
| | | | llvm-svn: 24739
* Add operand info for F3_[12] instructions, getting V8 back to basic ↵Chris Lattner2005-12-162-98/+198
| | | | | | | | | functionality. With this, Regression/CodeGen/SparcV8/basictest.ll now passes. Lets hear it for regression tests :) llvm-svn: 24738
* Remove JIT support, which doesn't work.Chris Lattner2005-12-165-295/+3
| | | | llvm-svn: 24736
* add some simple operand infoChris Lattner2005-12-161-7/+8
| | | | llvm-svn: 24735
* Update the darwin handling of linkonce & weak functions and GV stubs. ThisChris Lattner2005-12-161-57/+63
| | | | | | should work in all permutations. llvm-svn: 24728
* Don't globalize internal functionsChris Lattner2005-12-161-1/+2
| | | | llvm-svn: 24727
* * Promote all 1 bit entities to 8 bit.Evan Cheng2005-12-154-114/+9
| | | | | | | * Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit zextload. llvm-svn: 24726
* Added frameindex, constpool, globaladdr, and externalsym as root nodes ofEvan Cheng2005-12-151-2/+3
| | | | | | leaaddr. llvm-svn: 24724
* Added constpool, frameindex, and externalsym nodes.Evan Cheng2005-12-151-3/+9
| | | | llvm-svn: 24723
* Handling zero extension of 1 bit value.Evan Cheng2005-12-151-17/+128
| | | | llvm-svn: 24722
* Use MOV8rm to load 1 bit value.Evan Cheng2005-12-151-0/+3
| | | | llvm-svn: 24721
* Remove a now unused statistic.Nate Begeman2005-12-141-1/+0
| | | | llvm-svn: 24720
* Use the new predicate support that Evan Cheng added to remove some codeNate Begeman2005-12-142-57/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | from the DAGToDAG cpp file. This adds pattern support for vector and scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and does the right thing in the presence of -disable-excess-fp-precision. Allows us to match: void %foo(<4 x float> * %a) { entry: %tmp1 = load <4 x float> * %a; %tmp2 = mul <4 x float> %tmp1, %tmp1 %tmp3 = add <4 x float> %tmp2, %tmp1 store <4 x float> %tmp3, <4 x float> *%a ret void } As: _foo: li r2, 0 lvx v0, r2, r3 vmaddfp v0, v0, v0, v0 stvx v0, r2, r3 blr Or, with llc -disable-excess-fp-precision, _foo: li r2, 0 lvx v0, r2, r3 vxor v1, v1, v1 vmaddfp v1, v0, v0, v1 vaddfp v0, v1, v0 stvx v0, r2, r3 blr llvm-svn: 24719
* Fixed a typo: line 2323: MOVSX16rm8 -> MOVZX16rm8. This was the cause fo ↵Evan Cheng2005-12-141-1/+1
| | | | | | 12/14/2005 hbd failure. llvm-svn: 24717
* Added predicate !NoExcessFPPrecision to FMADD, FMADDS, FMSUB, and FMSUBS.Evan Cheng2005-12-141-4/+11
| | | | llvm-svn: 24716
* Added support to specify predicates.Evan Cheng2005-12-142-2/+17
| | | | llvm-svn: 24715
* Fixed extload type profile. The 4th operand is a ValueType node with typeEvan Cheng2005-12-141-2/+1
| | | | | | OtherVT, it cannot be compare to type of 1st operand which is an integer type. llvm-svn: 24713
* Added sext and zext patterns.Evan Cheng2005-12-141-9/+34
| | | | llvm-svn: 24705
* Added sextld + zextld DAG nodes.Evan Cheng2005-12-141-0/+17
| | | | llvm-svn: 24703
* Add support for fmul node of type v4f32.Nate Begeman2005-12-142-0/+21
| | | | | | | | | | | | | | | | | | | | | | void %foo(<4 x float> * %a) { entry: %tmp1 = load <4 x float> * %a; %tmp2 = mul <4 x float> %tmp1, %tmp1 store <4 x float> %tmp2, <4 x float> *%a ret void } Is selected to: _foo: li r2, 0 lvx v0, r2, r3 vxor v1, v1, v1 vmaddfp v0, v0, v0, v1 stvx v0, r2, r3 blr llvm-svn: 24701
* Prepare support for AltiVec multiply, divide, and sqrt.Nate Begeman2005-12-133-2/+19
| | | | llvm-svn: 24700
* Add load + store folding srl and sra patterns.Evan Cheng2005-12-131-12/+32
| | | | llvm-svn: 24696
* Use the shared asmprinter code for printing special llvm globalsChris Lattner2005-12-133-71/+10
| | | | llvm-svn: 24695
* Add ELF and darwin support for static ctors and dtorsChris Lattner2005-12-132-0/+40
| | | | llvm-svn: 24693
* reindent a loop, unswitch a loop. No functionality changesChris Lattner2005-12-131-105/+109
| | | | llvm-svn: 24692
* Beautify a few patterns.Evan Cheng2005-12-131-15/+15
| | | | llvm-svn: 24690
* Some shl patterns which do load + store folding.Evan Cheng2005-12-131-6/+16
| | | | llvm-svn: 24689
* A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 ↵Evan Cheng2005-12-131-12/+18
| | | | | | addr:$src). Only to improve readibility. llvm-svn: 24688
* Add and, or, and xor patterns which fold load + stores.Evan Cheng2005-12-131-41/+82
| | | | llvm-svn: 24687
* Add inc + dec patterns which fold load + stores.Evan Cheng2005-12-131-6/+12
| | | | llvm-svn: 24686
* Add neg and not patterns which fold load + stores.Evan Cheng2005-12-131-6/+12
| | | | llvm-svn: 24685
* Missed a couple redundant explicit type casts.Evan Cheng2005-12-131-3/+3
| | | | llvm-svn: 24684
* Fix some bad choice of names: i16SExt8 ->i16immSExt8, etc.Evan Cheng2005-12-131-34/+47
| | | | llvm-svn: 24683
* * Split immSExt8 to i16SExt8 and i32SExt8 for i16 and i32 immediate operands.Evan Cheng2005-12-131-27/+33
| | | | | | | This enables the removal of some explicit type casts. * Rename immZExt8 to i16ZExt8 as well. llvm-svn: 24682
* Add some integer mul patterns.Evan Cheng2005-12-121-11/+17
| | | | llvm-svn: 24681
* Add some sub patterns.Evan Cheng2005-12-121-13/+24
| | | | llvm-svn: 24675
* When SelectLEAAddr() fails, it shouldn't cause the side effect of having theEvan Cheng2005-12-121-17/+48
| | | | | | base or index operands being selected. llvm-svn: 24674
* For ISD::RET, if # of operands >= 2, try selection the real data dep. operandEvan Cheng2005-12-121-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | first before the chain. e.g. int X; int foo(int x) { x += X + 37; return x; } If chain operand is selected first, we would generate: movl X, %eax movl 4(%esp), %ecx leal 37(%ecx,%eax), %eax rather than movl $37, %eax addl 4(%esp), %eax addl X, %eax which does not require %ecx. (Due to ADD32rm not matching.) llvm-svn: 24673
* fix FP selectsAndrew Lenharth2005-12-122-14/+14
| | | | llvm-svn: 24672
* remove some never-completed and now-obsolete code.Chris Lattner2005-12-123-358/+0
| | | | llvm-svn: 24671
* Add a few more add / store patterns. e.g. ADD32mi8.Evan Cheng2005-12-121-10/+18
| | | | llvm-svn: 24670
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