summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* Move XCore from getRegClassForInlineAsmConstraint toEric Christopher2011-06-292-17/+14
| | | | | | | | getRegForInlineAsmConstraint. Part of rdar://9643582 llvm-svn: 134080
* Use getRegForInlineAsmConstraint instead of custom defining regclassesEric Christopher2011-06-292-56/+24
| | | | | | | | via vectors. Part of rdar://9643582 llvm-svn: 134079
* Fix CMake build.NAKAMURA Takumi2011-06-291-1/+0
| | | | llvm-svn: 134055
* Sink SubtargetFeature and TargetInstrItineraries (renamed ↵Evan Cheng2011-06-298-398/+8
| | | | | | MCInstrItineraries) into MC. llvm-svn: 134049
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-2828-59/+58
| | | | llvm-svn: 134030
* Hide more details in tablegen generated MCRegisterInfo ctor function.Evan Cheng2011-06-2813-25/+13
| | | | llvm-svn: 134027
* Add MCInstrInfo registeration machinery.Evan Cheng2011-06-281-0/+6
| | | | llvm-svn: 134026
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-2862-87/+112
| | | | llvm-svn: 134024
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-2838-470/+469
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Clean up the handling of the x87 fp stack to make it more robust.Jakob Stoklund Olesen2011-06-286-227/+362
| | | | | | | | | | | | | | | | | | | | Drop the FpMov instructions, use plain COPY instead. Drop the FpSET/GET instruction for accessing fixed stack positions. Instead use normal COPY to/from ST registers around inline assembly, and provide a single new FpPOP_RETVAL instruction that can access the return value(s) from a call. This is still necessary since you cannot tell from the CALL instruction alone if it returns anything on the FP stack. Teach fast isel to use this. This provides a much more robust way of handling fixed stack registers - we can tolerate arbitrary FP stack instructions inserted around calls and inline assembly. Live range splitting could sometimes break x87 code by inserting spill code in unfortunate places. As a bonus we handle floating point inline assembly correctly now. llvm-svn: 134018
* Remove warning: 'c0' may be used uninitialized in this function.Chad Rosier2011-06-281-1/+2
| | | | llvm-svn: 134014
* Implement ISD::VAARG lowering on PPC32.Roman Divacky2011-06-281-5/+123
| | | | llvm-svn: 134005
* Fix cmake build.Rafael Espindola2011-06-281-1/+1
| | | | llvm-svn: 133989
* ARM Thumb2 asm syntax optional destination operand for binary operators.Jim Grosbach2011-06-281-9/+29
| | | | | | | | | | | | | When the destination operand is the same as the first source register operand for arithmetic instructions, the destination operand may be omitted. For example, the following two instructions are equivalent: and r1, #ff and r1, r1, #ff rdar://9672867 llvm-svn: 133973
* ARM Assembly support for Thumb mov-immediate.Jim Grosbach2011-06-273-4/+40
| | | | | | | | | | | Correctly parse the forms of the Thumb mov-immediate instruction: 1. 8-bit immediate 0-255. 2. 12-bit shifted-immediate. The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic, but is not yet supported. More parser logic necessary there due to fixups. llvm-svn: 133966
* ARM Asm parsing of Thumb2 move immediate.Jim Grosbach2011-06-271-2/+3
| | | | | | | Thumb2 MOV mnemonic can accept both cc_out and predication. We don't (yet) encode the instruction properly, but this gets the parsing part. llvm-svn: 133945
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-276-29/+28
| | | | llvm-svn: 133944
* Add exception necessitated by 133938.Jim Grosbach2011-06-271-1/+1
| | | | llvm-svn: 133939
* ARM assembly carry set/clear condition code aliases for 'hi/lo'Jim Grosbach2011-06-271-0/+2
| | | | llvm-svn: 133938
* ARM assembler support for ldmfd/stmfd mnemonics.Jim Grosbach2011-06-271-0/+2
| | | | llvm-svn: 133936
* ARM assembler support for vpush/vpop.Jim Grosbach2011-06-271-0/+9
| | | | | | | | | Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple writeback instructions w/ SP as the base pointer. rdar://9683231 llvm-svn: 133932
* ARM Assembly syntax support for arithmetic implied dest operand.Jim Grosbach2011-06-271-7/+25
| | | | | | | | | | | | | When the destination operand is the same as the first source register operand for arithmetic instructions, the destination operand may be omitted. For example, the following two instructions are equivalent: sub r2, r2, #6 sub r2, #6 rdar://9682597 llvm-svn: 133925
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-2768-121/+130
| | | | | | into XXXGenRegisterInfo.inc. llvm-svn: 133922
* Grow the X86FloatingPoint register map to hold 16 registers.Jakob Stoklund Olesen2011-06-271-5/+15
| | | | | | | This allows for more live scratch registers which is needed to handle live ST registers before return and inline asm instructions. llvm-svn: 133903
* Replace dyn_cast<> with cast<> since the cast is already guarded by the ↵Chad Rosier2011-06-251-1/+1
| | | | | | necessary check. llvm-svn: 133874
* PTX: Reverting implementation of i8.Dan Bailey2011-06-257-296/+73
| | | | | | | | The .b8 operations in PTX are far more limiting than I first thought. The mov operation isn't even supported, so there's no way of converting a .pred value into a .b8 without going via .b16, which is not sensible. An improved implementation needs to use the fact that loads and stores automatically extend and truncate to implement support for EXTLOAD and TRUNCSTORE in order to correctly support boolean values. llvm-svn: 133873
* Enable tail call optimization in the presence of a byval (x86-32 and x86-64).Chad Rosier2011-06-251-0/+4
| | | | | | <rdar://problem/9483883> llvm-svn: 133858
* Unbreak CMake buildDouglas Gregor2011-06-251-0/+2
| | | | llvm-svn: 133853
* Add include guard.Evan Cheng2011-06-241-0/+5
| | | | llvm-svn: 133847
* Rename TargetDesc to MCTargetDescEvan Cheng2011-06-246-4/+3
| | | | llvm-svn: 133846
* Refactor MachO relocation generaration into the Target directories.Jim Grosbach2011-06-243-0/+885
| | | | | | | | | Move the target-specific RecordRelocation logic out of the generic MC MachObjectWriter and into the target-specific object writers. This allows nuking quite a bit of target knowledge from the supposedly target-independent bits in lib/MC. llvm-svn: 133844
* Fix cmake build.Rafael Espindola2011-06-241-0/+1
| | | | llvm-svn: 133830
* Hoist simple check above more complex checking to avoid unnecessary Chad Rosier2011-06-241-5/+5
| | | | | | overheads. No functional change intended. llvm-svn: 133824
* - Add MCRegisterInfo registration machinery. Also added x86 registration ↵Evan Cheng2011-06-242-0/+16
| | | | | | | | routines. - Rename TargetRegisterDesc to MCRegisterDesc. llvm-svn: 133820
* ARM movw/movt fixups need to mask the high bits.Jim Grosbach2011-06-241-3/+6
| | | | | | | | | | The fixup value comes in as the whole 32-bit value, so for the lo16 fixup, the upper bits need to be masked off. Previously we assumed the masking had already been done and asserted. rdar://9635991 llvm-svn: 133818
* PTX: Add support for i8 type and introduce associated .b8 registersDan Bailey2011-06-247-15/+291
| | | | | | The i8 type is required for boolean values, but can only use ld, st and mov instructions. The i1 type continues to be used for predicates. llvm-svn: 133814
* The Neon VCVT (between floating-point and fixed-point, Advanced SIMD) Chad Rosier2011-06-241-1/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | instructions can be used to match combinations of multiply/divide and VCVT (between floating-point and integer, Advanced SIMD). Basically the VCVT immediate operand that specifies the number of fraction bits corresponds to a floating-point multiply or divide by the corresponding power of 2. For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a combination of VMUL and VCVT (floating-point to integer) as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3 Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a combinations of VCVT (integer to floating-point) and VDIV as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vcvt.f32.s32 d16, d16 vdiv.f32 d16, d17, d16 becomes: vcvt.f32.s32 d16, d16, #3 llvm-svn: 133813
* PTX: Add preliminary support for outputting debug information in the form ofJustin Holewinski2011-06-241-0/+97
| | | | | | | | | | .file and .loc directives. Ideally, we would utilize the existing support in AsmPrinter for this, but I cannot find a way to get .file and .loc directives to print without the rest of the associated DWARF sections, which ptxas cannot handle. llvm-svn: 133812
* Change the chain input of nodes that load the address of a function. This changeAkira Hatanaka2011-06-241-4/+1
| | | | | | | | enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a pre-existing node instead of redundantly create a new node every time it is called. llvm-svn: 133811
* Prevent generation of redundant addiu instructions that compute address of Akira Hatanaka2011-06-241-1/+2
| | | | | | static variables or functions. llvm-svn: 133803
* PTX: Re-work target sm/compute selection and add some basic GPUJustin Holewinski2011-06-246-47/+121
| | | | | | targets: g80, gt200, gf100(fermi) llvm-svn: 133799
* Fix CellSPU CMakeList.txt.Rafael Espindola2011-06-241-1/+1
| | | | llvm-svn: 133792
* Fix CellSPU CMakeLists.txtEvan Cheng2011-06-241-2/+3
| | | | llvm-svn: 133787
* Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng2011-06-2444-104/+188
| | | | | | | | | | | | target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. llvm-svn: 133782
* Add support for movntil/movntiq mnemonics. Reported on llvmdev.Eli Friedman2011-06-231-2/+2
| | | | llvm-svn: 133759
* Rename TargetOptions::StackAlignment to StackAlignmentOverride.Evan Cheng2011-06-232-3/+3
| | | | llvm-svn: 133739
* Remove TargetOptions.h dependency from ARMSubtarget.Evan Cheng2011-06-232-5/+4
| | | | llvm-svn: 133738
* PTX: Always use registers for return values, but use .param space for deviceJustin Holewinski2011-06-236-108/+725
| | | | | | | | | | | parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers llvm-svn: 133736
* PTX: Whitespace fixes and remove commented out codeJustin Holewinski2011-06-232-36/+0
| | | | llvm-svn: 133734
* PTX: Prevent DCE from eliminating st.param calls, and unify the handling ofJustin Holewinski2011-06-235-107/+78
| | | | | | | st.param and ld.param FIXME: Test cases still need to be updated llvm-svn: 133733
OpenPOWER on IntegriCloud