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* add a noteChris Lattner2007-08-201-0/+18
| | | | llvm-svn: 41178
* MipsHi now has ouput flagBruno Cardoso Lopes2007-08-181-91/+185
| | | | | | | | | | | | MipsAdd SDNode created to add support to an Add opcode which supports input flag Added an instruction itinerary to all instruction classes Added branches with zero cond codes Now call clobbers all non-callee saved registers Call w/ register support added Added DelaySlot to branch and load instructions Added patterns to handle all setcc, brcond/setcc and MipsAdd instructions llvm-svn: 41161
* Fixed stack frame addressing bugBruno Cardoso Lopes2007-08-181-8/+8
| | | | llvm-svn: 41160
* support for Schedule included on Mips.tdBruno Cardoso Lopes2007-08-182-28/+15
| | | | llvm-svn: 41159
* Removed LowerRETURADDR, fixed small bug into LowerRET, LowerGlobalAddressBruno Cardoso Lopes2007-08-182-17/+11
| | | | | | fixed to generate instructions (add, lui) glued! llvm-svn: 41158
* Couple of small changes. Delay Slot handle header declared. Bruno Cardoso Lopes2007-08-182-2/+3
| | | | | | Newline added after macros at function init on generated asm! llvm-svn: 41157
* Added InstrItinClass support for instruction formatsBruno Cardoso Lopes2007-08-181-9/+10
| | | | llvm-svn: 41156
* Branch Analysis and InsertNoop inserted into header filesBruno Cardoso Lopes2007-08-181-2/+36
| | | | llvm-svn: 41155
* createMipsDelaySlotFillerPass added to mips codegen runtime Bruno Cardoso Lopes2007-08-181-2/+2
| | | | llvm-svn: 41154
* Added Branch Analysis support Bruno Cardoso Lopes2007-08-181-5/+234
| | | | | | Added InsertNoop support llvm-svn: 41153
* LowerRETURNADDR removed since it was wrong and does not have utility yet!Bruno Cardoso Lopes2007-08-181-2/+3
| | | | | | MipsAdd opcode added llvm-svn: 41152
* InstrItineraryData support on added.Bruno Cardoso Lopes2007-08-181-2/+8
| | | | | | Added Mips3 ISA feature (needed when supporting R4000 machines) llvm-svn: 41151
* A Pass to insert Nops on intructions with DelaySlotBruno Cardoso Lopes2007-08-181-0/+77
| | | | llvm-svn: 41150
* Mips generic fallback instruction schedule support!Bruno Cardoso Lopes2007-08-181-0/+63
| | | | llvm-svn: 41149
* Move ReturnAddrIndex variable to X86MachineFunctionInfo structure. This fixedAnton Korobeynikov2007-08-153-14/+24
| | | | | | hard to catch bugs with retaddr lowering llvm-svn: 41104
* add a note.Chris Lattner2007-08-151-0/+3
| | | | llvm-svn: 41103
* Fix a typo pointd out by Maarten ter Huurne.Evan Cheng2007-08-131-1/+1
| | | | llvm-svn: 41059
* When x86 addresses matching exceeds its recursion limit, check toDan Gohman2007-08-131-6/+12
| | | | | | | see if the base register is already occupied before assuming it can be used. This fixes bogus code generation in the accompanying testcase. llvm-svn: 41049
* Fix PR1607Chris Lattner2007-08-131-3/+3
| | | | llvm-svn: 41048
* expand a noteChris Lattner2007-08-111-3/+22
| | | | llvm-svn: 41021
* With evan's explicit flag representation, hopefully we will finally beChris Lattner2007-08-111-1/+1
| | | | | | | | | able to 3-addressify away stuff like this: movl %ecx, %eax decl %eax llvm-svn: 41020
* 64-bit SSSE3 ops that use MMX registers don't require 16-byte alignment.Bill Wendling2007-08-111-6/+21
| | | | | | Make a 'memop' pattern just for them. llvm-svn: 41017
* Use subregs to improve any_extend code generation when feasible.Christopher Lamb2007-08-102-16/+33
| | | | llvm-svn: 41013
* Increase efficiency of sign_extend_inreg by using subregisters for ↵Christopher Lamb2007-08-103-49/+89
| | | | | | truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)). llvm-svn: 41010
* Edit README in light of previous LEA16 commit.Christopher Lamb2007-08-101-3/+1
| | | | llvm-svn: 41009
* Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via ↵Christopher Lamb2007-08-101-10/+47
| | | | | | subregisters when 16-bit LEA is disabled. llvm-svn: 41007
* propagate struct size and alignment of byval arguments to the DAGRafael Espindola2007-08-101-1/+6
| | | | llvm-svn: 40986
* For kicks, I though it would be fun to use the correct opcode.Bill Wendling2007-08-101-31/+32
| | | | llvm-svn: 40985
* Adding SSSE3 intrinsics.Bill Wendling2007-08-101-17/+284
| | | | llvm-svn: 40982
* Temporarily backing out this change until we know why some dejagnu tests are ↵Evan Cheng2007-08-091-3/+2
| | | | | | failing. llvm-svn: 40973
* divb / mulb outputs to ah. Under x86-64 it's not legal to read ah if the ↵Evan Cheng2007-08-092-4/+46
| | | | | | instruction requires a rex prefix (i.e. outputs to r8b, etc.). So issue shift right by 8 on AX and then truncate it to 8 bits instead. llvm-svn: 40972
* GR16_ sub-register class should be GR8_, not GR8. That is, it should only be ↵Evan Cheng2007-08-091-3/+4
| | | | | | 8-bit registers in 32-bit mode. Ditto for GR32_. llvm-svn: 40970
* long double 9 of N. This finishes up the X86-32 bitsDale Johannesen2007-08-091-1/+13
| | | | | | | | (constants are still not handled). Adds ConvertActions to control fp-to-fp conversions (these are currently defaulted for all other targets, so no changes there). llvm-svn: 40958
* Fix arguments for some Altivec instructions. From SWB.Dale Johannesen2007-08-091-9/+15
| | | | llvm-svn: 40957
* Fix spelling of mtvscr and mfvscr.Dale Johannesen2007-08-071-2/+2
| | | | llvm-svn: 40908
* Long double patch 8 of N: make it partially work inDale Johannesen2007-08-073-100/+100
| | | | | | | | | | | SSE mode (all but conversions <-> other FP types, I think): >>Do not mark all-80-bit operations as "Requires[FPStack]" (which really means "not SSE"). >>Refactor load-and-extend to facilitate this. >>Update comments. >>Handle long double in SSE when computing FP_REG_KILL. llvm-svn: 40906
* Initial JIT support for ARM by Raul Fernandes Herbster.Evan Cheng2007-08-079-275/+889
| | | | llvm-svn: 40887
* Long double patch 7 of N, unless I lost count:). Dale Johannesen2007-08-073-1/+37
| | | | | | | | Last x87 bits for full functionality (not thoroughly tested, and long doubles do not work in SSE modes at all - use -mcpu=i486 for now) llvm-svn: 40886
* Replace 4-line function with 10-line version per review comment.Dale Johannesen2007-08-061-4/+10
| | | | llvm-svn: 40881
* Move lengthy conditional down 1 level per review comment.Dale Johannesen2007-08-062-5/+6
| | | | llvm-svn: 40878
* Get X86 long double calling convention to workDale Johannesen2007-08-064-3/+34
| | | | | | | (on Darwin, anyway). Fix some table omissions for LD arithmetic. llvm-svn: 40877
* Make 80-bit store maintain simulated FP stack correctly.Dale Johannesen2007-08-061-1/+2
| | | | llvm-svn: 40868
* Fix minor doxygen nits.Reid Spencer2007-08-051-3/+3
| | | | llvm-svn: 40854
* Long double patch 4 of N: initial x87 implementation.Dale Johannesen2007-08-058-6/+162
| | | | | | Lots of problems yet but some simple things work. llvm-svn: 40847
* This is the patch to provide clean intrinsic function overloading support in ↵Chandler Carruth2007-08-041-2/+2
| | | | | | | | LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future. This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported. llvm-svn: 40807
* Make x86 long double alignment 32 for everything butDale Johannesen2007-08-031-1/+3
| | | | | | Darwin (which makes size within a struct==96) llvm-svn: 40796
* long double patch 2 of N. Handle it in TargetData.Dale Johannesen2007-08-036-7/+19
| | | | | | | (I've tried to get the info right for all targets, but I'm not expert on all of them - check yours.) llvm-svn: 40792
* add an observationChris Lattner2007-08-031-0/+27
| | | | llvm-svn: 40772
* More explicit keywords.Dan Gohman2007-08-026-6/+6
| | | | llvm-svn: 40757
* Fix the alignment requirements of several unpck and shuf instructions.Dan Gohman2007-08-022-13/+21
| | | | | | | | Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's memory operand alignment can be tested as well, with a fix to avoid breaking MMX's use of isPSHUFDMask. llvm-svn: 40756
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