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* AVX-512: aligned / unaligned load and store for 512-bit integer vectors.Elena Demikhovsky2013-10-222-30/+36
| | | | llvm-svn: 193156
* Replace (V)MOVZDI2PDIrr/rm instructions with patterns that select ↵Craig Topper2013-10-222-37/+22
| | | | | | (V)MOVDI2PDIrr/rm. llvm-svn: 193146
* ARM: Thumb2 copy for GPRPair needs to use thumb instructions.Jim Grosbach2013-10-221-1/+1
| | | | | | | | Use tMOVr instead of plain MOVr. rdar://15193017 llvm-svn: 193139
* ARM: Clean up copyPhysReg() a bit.Jim Grosbach2013-10-221-27/+47
| | | | | | No functional change, just cleaning things up for readability. llvm-svn: 193138
* [AArch64] Add the constraint to NEON scalar mla/mls instructions.Chad Rosier2013-10-211-6/+30
| | | | llvm-svn: 193117
* X86 vector element shift-by-immediate instructions take i8 immediates. MakeLang Hames2013-10-213-60/+73
| | | | | | | | | | | | | | the instruction defenitions and ISEL reflect this. Prior to this patch these instructions took an i32i8imm, and the high bits were dropped during encoding. This led to incorrect behavior for shifts by immediates higher than 255. This patch fixes that issue by detecting large immediate shifts and returning constant zero (for logical shifts) or capping the shift amount at an encodable value (for arithmetic shifts). Fixes <rdar://problem/14968098> llvm-svn: 193096
* AVX-512: MUL operation lowering for v8i64Elena Demikhovsky2013-10-211-3/+4
| | | | llvm-svn: 193083
* [mips][msa] Direct Object Emission support for LD/ST instructions.Matheus Almeida2013-10-213-24/+56
| | | | llvm-svn: 193082
* [mips][msa] Direct Object Emission support for LDI instructions.Matheus Almeida2013-10-212-8/+13
| | | | llvm-svn: 193081
* [mips][msa] Direct Object Emission support for MOVE.v.Matheus Almeida2013-10-212-2/+7
| | | | llvm-svn: 193080
* [mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. Matheus Almeida2013-10-215-14/+137
| | | | | | | | These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. llvm-svn: 193078
* [mips][msa] Direct Object Emission of SPLAT instruction.Matheus Almeida2013-10-211-12/+16
| | | | llvm-svn: 193077
* [mips][msa] Fix definition of SLD instruction.Matheus Almeida2013-10-212-8/+36
| | | | | | | The second parameter of the SLD intrinsic is the number of columns (GPR) to slide left the source array. llvm-svn: 193076
* Mark some command line flags as hiddenNadav Rotem2013-10-185-11/+11
| | | | llvm-svn: 193013
* MC asm parser: allow ?'s in symbol names, and handle @'s in names in MS asmHans Wennborg2013-10-181-0/+2
| | | | | | | | | | | | | | | | | | | | This is another (final?) stab at making us able to parse our own asm output on Windows. Symbols on Windows often contain @'s and ?'s in their names. Our asm parser didn't like this. ?'s were not allowed, and @'s were intepreted as trying to reference PLT/GOT/etc. We can't just add quotes around the bad names, since e.g. for MinGW, we use gas to assemble, and it doesn't like quotes in some places (notably in .def directives). This commit makes us allow ?'s in symbol names, and @'s in symbol names for MS assembly. Differential Revision: http://llvm-reviews.chandlerc.com/D1978 llvm-svn: 193000
* Pure refactoring change.Richard Barton2013-10-181-73/+86
| | | | | | Patch by Artyom Skrobov. llvm-svn: 192977
* R600: Remove \ at EOL from ascii art comments.Benjamin Kramer2013-10-181-4/+4
| | | | | | | Completely harmless, but GCC likes to warn about it even when the next line is a comment. llvm-svn: 192974
* Add hint disassembly syntax for 16-bit Thumb hint instructions.Richard Barton2013-10-184-25/+23
| | | | | | Patch by Artyom Skrobov llvm-svn: 192972
* [AArch64] Add support for NEON scalar extract narrow instructions.Chad Rosier2013-10-181-0/+48
| | | | llvm-svn: 192970
* Add hardware division as a default feature on Cortex-A15. Also add test ↵Silviu Baranga2013-10-182-2/+3
| | | | | | cases to check this, and change diagnostics for the hwdiv-arm feature to something useful. llvm-svn: 192963
* Revert "Re-commit r192758 - MC: quote tricky symbol names in asm output"Hans Wennborg2013-10-181-3/+1
| | | | | | | | | | | | | | | | | This caused the clang-native-mingw32-win7 buildbot to break. The assembler was complaining about the following lines that were showing up in the asm for CrashRecoveryContext.cpp: movl $"__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4", 4(%eax) calll "_AddVectoredExceptionHandler@8" .def "__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4"; "__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4": calll "_RemoveVectoredExceptionHandler@4" Reverting for now. llvm-svn: 192940
* 17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targetsDavid Peixotto2013-10-171-7/+108
| | | | | | | | | | | | | | | | | | | | | | | | This commit implements the correct lowering of the COPY_STRUCT_BYVAL_I32 pseudo-instruction for thumb1 targets. Previously, the lowering of COPY_STRUCT_BYVAL_I32 generated the post-increment forms of ldr/ldrh/ldrb instructions. Thumb1 does not have the post-increment form of these instructions so the generated assembly contained invalid instructions. Passing the generated assembly to gcc caused it to complain with an error like this: Error: cannot honor width suffix -- `ldrb r3,[r0],#1' and the integrated assembler would generate an object file with an invalid instruction encoding. This commit contains a small test case that demonstrates the problem with thumb1 targets as well as an expanded test case that more throughly tests the lowering of byval struct passing for arm, thumb1, and thumb2 targets. llvm-svn: 192916
* Refactor lowering for COPY_STRUCT_BYVAL_I32David Peixotto2013-10-171-170/+460
| | | | | | | | | | | | | | | | | | This commit refactors the lowering of the COPY_STRUCT_BYVAL_I32 pseudo-instruction in the ARM backend. We introduce a new helper class that encapsulates all of the operations needed during the lowering. The operations are implemented for each subtarget in different subclasses. Currently only arm and thumb2 subtargets are supported. This refactoring was done to easily implement support for thumb1 subtargets. This initial patch does not add support for thumb1, but is only a refactoring. A follow on patch will implement the support for thumb1 subtargets. No intended functionality change. llvm-svn: 192915
* llvm-c: Add LLVMIntPtrType{,ForAS}InContextAnders Waldenborg2013-10-171-0/+8
| | | | | | | | | | | | All of the Core API functions have versions which accept explicit context, in addition to ones which work on global context. This commit adds functions which accept explicit context to the Target API for consistency. Patch by Peter Zotov Differential Revision: http://llvm-reviews.chandlerc.com/D1912 llvm-svn: 192913
* [AArch64] Add support for NEON scalar three register different instructionChad Rosier2013-10-172-0/+57
| | | | | | | | class. The instruction class includes the signed saturating doubling multiply-add long, signed saturating doubling multiply-subtract long, and the signed saturating doubling multiply long instructions. llvm-svn: 192908
* [mips][msa] Added lsa instructionDaniel Sanders2013-10-173-0/+30
| | | | llvm-svn: 192895
* [mips][msa] Removed ldx.[bhwd] and stx.[bhwd].Daniel Sanders2013-10-172-59/+0
| | | | | | | | These were present in a previous version of the MSA spec but are not present in the published version. There is no hardware that uses these instructions. llvm-svn: 192888
* llvm-c: Don't assert in LLVMTargetMachineEmitToFile on nonexistent fileAnders Waldenborg2013-10-171-1/+1
| | | | | | | | | | | | Error handling code for raw_fd_ostream constructor is present, but never used, because formatted_raw_ostream will always assert on closed fd's before. Patch by Peter Zotov Differential Revision: http://llvm-reviews.chandlerc.com/D1909 llvm-svn: 192881
* [mips][msa] Correct definition order of ftrunc_[su], ftint_[su], and ftq.Daniel Sanders2013-10-171-22/+22
| | | | | | | | Define these three instructions in alphabetical order (like the rest of the file). No functional change. llvm-svn: 192880
* llvm-c: Return NULL from LLVMGetFirstTarget instead of assertingAnders Waldenborg2013-10-171-2/+6
| | | | | | | | | | | | If no targets are registered, LLVMGetFirstTarget currently fails with an assertion. This patch makes it return NULL instead, similarly to how LLVMGetNextTarget would. Patch by Peter Zotov Differential Revision: http://llvm-reviews.chandlerc.com/D1908 llvm-svn: 192878
* x86: Move bitcasts outside concat_vector.Jim Grosbach2013-10-171-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consider the following: typedef unsigned short ushort4U __attribute__((ext_vector_type(4), aligned(2))); typedef unsigned short ushort4 __attribute__((ext_vector_type(4))); typedef unsigned short ushort8 __attribute__((ext_vector_type(8))); typedef int int4 __attribute__((ext_vector_type(4))); int4 __bbase_cvt_int(ushort4 v) { ushort8 a; a.lo = v; return _mm_cvtepu16_epi32(a); } This generates the, not unreasonable, IR: define <4 x i32> @foo0(double %v.coerce) nounwind ssp { %tmp = bitcast double %v.coerce to <4 x i16> %tmp1 = shufflevector <4 x i16> %tmp, <4 x i16> undef, <8 x i32> <i32 %0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %tmp2 = tail call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp1) ret <4 x i32> %tmp2 } The problem is when type legalization gets hold of the v4i16. It legalizes that by spilling to the stack, then doing a zero-extending load. Things go even more silly from there, ending up with something like: _foo0: movsd %xmm0, -8(%rsp) <== Spill to the stack. movq -8(%rsp), %xmm0 <== Reload it right back out. pmovzxwd %xmm0, %xmm1 <== Here's what we actually asked for. pblendw $1, %xmm1, %xmm0 <== We don't need this at all pmovzxwd %xmm0, %xmm0 <== We already did this ret The v8i8 to v8i16 zext intrinsic gives even worse results, with two table lookups via pshufb instructions(!!). To avoid all that, we can move the bitcasting until after we've formed the wider (legal) vector type. Then our normal codegen flows along nicely and we get the expected: _foo0: pmovzxwd %xmm0, %xmm0 ret rdar://15245794 llvm-svn: 192866
* Re-commit r192758 - MC: quote tricky symbol names in asm outputHans Wennborg2013-10-171-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The reason this got reverted was that the @feat.00 symbol which was emitted for every TU became quoted, and on cygwin/mingw we use the gas assembler which couldn't handle the quotes. This commit fixes the problem by only emitting @feat.00 for win32, where we use clang -cc1as to assemble. gas would just drop this symbol anyway, so there is no loss there. With @feat.00 gone, there shouldn't be quoted symbols showing up on cygwin since it uses the Itanium ABI, which doesn't put these funny characters in symbols. > Because of win32 mangling, we produce symbol and section names with > funny characters in them, most notably @ characters. > > MC would choke on trying to parse its own assembly output. This patch addresses > that by: > > - Making @ trigger quoting of symbol names > - Also quote section names in the same way > - Just parse section names like other identifiers (to allow for quotes) > - Don't assume @ signifies a symbol variant if it is in a string. llvm-svn: 192859
* [AArch64] Add support for NEON scalar negate instruction.Chad Rosier2013-10-161-0/+4
| | | | llvm-svn: 192843
* [AArch64] Add support for NEON scalar absolute value instruction.Chad Rosier2013-10-161-8/+21
| | | | llvm-svn: 192842
* Add support for the VSX target attribute. No functional changeEric Christopher2013-10-162-0/+3
| | | | | | as we don't actually use it to emit any code yet. llvm-svn: 192837
* Enabling 3DNow! prefetch instruction for a few AMD processors: bobcat, jaguar,Yunzhong Gao2013-10-162-7/+7
| | | | | | | | | bulldozer and piledriver. Support for the instruction itself seems to have already been added in r178040. Differential Revision: http://llvm-reviews.chandlerc.com/D1933 llvm-svn: 192828
* R600: Fix a crash in the AMDILCFGStructurizerTom Stellard2013-10-161-2/+68
| | | | | | | | | | We were calling llvm_unreachable() when failing to optimize the branch into if case. However, it is still possible for us to structurize the CFG by duplicating blocks even if this optimization fails. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 192813
* R600: Remove some dead code from the AMDILCFGStructurizerTom Stellard2013-10-161-21/+4
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 192812
* Fix comment.Chad Rosier2013-10-161-1/+1
| | | | llvm-svn: 192805
* Assert on duplicate registration. Don't depend on function pointer equality.Rafael Espindola2013-10-161-3/+0
| | | | | | | | | | | | | | | | | | | | Before this patch we would assert when building llvm as multiple shared libraries (cmake's BUILD_SHARED_LIBS). The problem was the line if (T.AsmStreamerCtorFn == Target::createDefaultAsmStreamer) which returns false because of -fvisibility-inlines-hidden. It is easy to fix just this one case, but I decided to try to also make the registration more strict. It looks like the old logic for ignoring followup registration was just a temporary hack that outlived its usefulness. This patch converts the ifs to asserts, fixes the few cases that were registering twice and makes sure all the asserts compare with null. Thanks for Joerg for reporting the problem and reviewing the patch. llvm-svn: 192803
* [AArch64] Add support for NEON scalar signed saturating accumulated of unsignedChad Rosier2013-10-161-2/+52
| | | | | | value and unsigned saturating accumulate of signed value instructions. llvm-svn: 192800
* [SystemZ] Handle extensions in RxSBG optimizationsRichard Sandiford2013-10-161-8/+26
| | | | | | | The input to an RxSBG operation can be narrower as long as the upper bits are don't care. This fixes a FIXME added in r192783. llvm-svn: 192790
* [SystemZ] Improve handling of SETCCRichard Sandiford2013-10-165-4/+120
| | | | | | | | We previously used the default expansion to SELECT_CC, which in turn would expand to "LHI; BRC; LHI". In most cases it's better to use an IPM-based sequence instead. llvm-svn: 192784
* Add a MCAsmInfoELF class and factor some code into it.Rafael Espindola2013-10-1620-32/+21
| | | | | | We had a MCAsmInfoCOFF, but no common class for all the ELF MCAsmInfos before. llvm-svn: 192760
* Move .ident handling to MCStreamer.Rafael Espindola2013-10-161-0/+1
| | | | | | | | No functionality change, but exposes the API so that codegen can use it too. Patch by Katya Romanova. llvm-svn: 192757
* Fix typoMatt Arsenault2013-10-151-1/+1
| | | | llvm-svn: 192752
* Fix missing C++ mode thing in headerMatt Arsenault2013-10-151-1/+1
| | | | llvm-svn: 192751
* Enable MI Sched for x86.Andrew Trick2013-10-151-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
* R600/SI: Remove some leftover MI dump callVincent Lejeune2013-10-152-2/+0
| | | | llvm-svn: 192743
* [AArch64] Add support for NEON scalar signed saturating absolute value andChad Rosier2013-10-151-1/+45
| | | | | | scalar signed saturating negate instructions. llvm-svn: 192733
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