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* [AVX512] Add non-temporal store patterns for v16i32/v32i16/v64i8.Craig Topper2016-05-081-0/+9
| | | | llvm-svn: 268889
* [AVX512] Add missing patterns for non-temporal stores of 128/256-bit ↵Craig Topper2016-05-081-0/+16
| | | | | | | | vXi8/vXi16/vXi32 when VLX is enabled. The equivalent AVX1/2 patterns are disabled by VLX. This caused regular stores to be emitted instead. llvm-svn: 268886
* [AVX512] Change predicates on some vXi16/vXi8 AVX store patterns so they ↵Craig Topper2016-05-081-16/+22
| | | | | | | | stay enabled unless VLX and BWI instructions are supported." Without this we could fail instruction selection if VLX was enabled, but BWI wasn't. llvm-svn: 268885
* [AVX512] Add VLX 128/256-bit SET0 operations that encode to 128/256-bit EVEX ↵Craig Topper2016-05-083-2/+15
| | | | | | encoded VPXORD so all 32 registers can be used. llvm-svn: 268884
* [X86] Remove extra patterns that check for BUILD_VECTOR of all 0s. These are ↵Craig Topper2016-05-082-24/+7
| | | | | | always canonicalized to v4i32/v8i32/v16i32 except for in SSE1 only when only v4f32 is supported. llvm-svn: 268880
* [X86] Promote several single precision FP libcalls on WindowsDavid Majnemer2016-05-081-10/+12
| | | | | | | | | | | | A number of libcalls don't exist in any particular lib but are, instead, defined in math.h as inline functions (even in C mode!). Don't rely on their existence when lowering @llvm.{cos,sin,floor,..}.f32, promote them instead. N.B. We had logic to handle FREM but were missing out on a number of others. This change generalizes the FREM handling. llvm-svn: 268875
* [X86] Lower 256-bit vector all-zero constants to v8i32 even with AVX1 only. ↵Craig Topper2016-05-082-11/+3
| | | | | | Either way a 256-bit VXORPS will be used. llvm-svn: 268873
* [X86] Add patterns for 256-bit non-temporal stores when only AVX1 is ↵Craig Topper2016-05-081-6/+20
| | | | | | supported. While there, add a predicate to the SSE2 patterns to avoid an ordering dependency. llvm-svn: 268872
* [X86] No need to avoid selecting AVX_SET0 for 256-bit integer types when ↵Craig Topper2016-05-081-23/+1
| | | | | | only AVX1 is supported. AVX_SET0 just expands to 256-bit VXORPS which is legal in AVX1. llvm-svn: 268871
* [ARM] Fix Scavenger assert due to underestimated stack sizeWeiming Zhao2016-05-081-5/+25
| | | | | | | | | | | | | | | | (re-apply r268810 as it exposed an uninitialized variable in ARM MFI. Patch 268868 should fix that.) Summary: Currently, when checking if a stack is "BigStack" or not, it doesn't count into spills and arguments. Therefore, LLVM won't reserve spill slot for this actually "BigStack". This may cause scavenger failure. Reviewers: rengolin Subscribers: vitalybuka, aemerson, rengolin, tberghammer, danalbert, srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D19896 llvm-svn: 268869
* Fix use-of-uninitialized-value of ARMMachineFunctionInfoWeiming Zhao2016-05-081-1/+1
| | | | | | | | | | | | Summary: Explicitly initialize ArgumentStackSize to prevent the msan failure. Reviewers: rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D20051 llvm-svn: 268868
* [X86] Fix InstAliases to not allow FARCALL32i/FARCALL16i/FARJMP32i/FARJMP16i ↵Craig Topper2016-05-071-8/+8
| | | | | | in 64-bit mode. llvm-svn: 268863
* [X86] Pulled out duplicate mask width calculation. NFCI.Simon Pilgrim2016-05-071-2/+3
| | | | llvm-svn: 268861
* [x86, BMI] add TLI hook for 'andn' and use it to simplify comparisonsSanjay Patel2016-05-072-0/+14
| | | | | | | | | | | | | | | | | | | | | For the sake of minimalism, this patch is x86 only, but I think that at least PPC, ARM, AArch64, and Sparc probably want to do this too. We might want to generalize the hook and pattern recognition for a target like PPC that has a full assortment of negated logic ops (orc, nand). Note that http://reviews.llvm.org/D18842 will cause this transform to trigger more often. For reference, this relates to: https://llvm.org/bugs/show_bug.cgi?id=27105 https://llvm.org/bugs/show_bug.cgi?id=27202 https://llvm.org/bugs/show_bug.cgi?id=27203 https://llvm.org/bugs/show_bug.cgi?id=27328 Differential Revision: http://reviews.llvm.org/D19087 llvm-svn: 268858
* MipsELFObjectWriter.cpp: Activate debug printer just for +Asserts. ↵NAKAMURA Takumi2016-05-071-0/+2
| | | | | | [-Wunused-function] llvm-svn: 268848
* Revert r268810 becase it brakes msan bot.Vitaly Buka2016-05-071-25/+5
| | | | | | | 16802==WARNING: MemorySanitizer: use-of-uninitialized-value lib/Target/ARM/ARMFrameLowering.cpp:1632 llvm-svn: 268833
* [X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr.Ahmed Bougacha2016-05-071-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
* [X86] Register and initialize the FixupBW pass.Ahmed Bougacha2016-05-073-8/+19
| | | | | | That lets us use it in MIR tests. llvm-svn: 268830
* [ARM] Fix Scavenger assert due to underestimated stack sizeWeiming Zhao2016-05-061-5/+25
| | | | | | | | | | | | | | | | | | | (this is resubmit of r268529 with minor refactoring. r268529 was reverted at r268536 due a memory sanitizer failure. I have not been able to reproduce that failure and I checked all the variable used in my change but I could not spot an issue. I did some refactoring and see if it will give a clearer hint) Summary: Currently, when checking if a stack is "BigStack" or not, it doesn't count into spills and arguments. Therefore, LLVM won't reserve spill slot for this actually "BigStack". This may cause scavenger failure. Reviewers: rengolin Subscribers: vitalybuka, aemerson, rengolin, tberghammer, danalbert, srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D19896 llvm-svn: 268810
* Revert "[X86] Add a new LOW32_ADDR_ACCESS_RBP register class."Quentin Colombet2016-05-062-14/+1
| | | | | | | | This reverts commit r268796. I believe it breaks test/CodeGen/X86/asm-mismatched-types.ll with: Cannot emit physreg copy instruction llvm-svn: 268799
* [X86] Add a new LOW32_ADDR_ACCESS_RBP register class.Quentin Colombet2016-05-062-1/+14
| | | | | | | | ABIs like NaCl uses 32-bit addresses but have 64-bit frame. The new register class reflects those constraints when choosing a register class for a address access. llvm-svn: 268796
* [X86] Rename the X32_ADDR_ACCESS register class into LOW32_ADDR_ACCESS.Quentin Colombet2016-05-062-8/+12
| | | | | | | | This register class may be used by any ABIs that uses x86_64 ISA while using 32-bit addresses, not just in X32 cases. Make sure the name reflects that. llvm-svn: 268795
* Revert r268760, it caused PR27670.Nico Weber2016-05-061-53/+0
| | | | llvm-svn: 268794
* [X86] Accept imp-defs of GR64 super-registers in FixupBW MOVrr.Ahmed Bougacha2016-05-061-5/+11
| | | | | | Testcase will follow shortly. llvm-svn: 268787
* [AMDGPU][llvm-mc] Some refactoring of .td filesArtem Tamazov2016-05-062-27/+27
| | | | | | | | | Some custom Operands and AsmOperandClasses moved to proper place. No functional changes. Differential Revision: http://reviews.llvm.org/D20012 llvm-svn: 268780
* [Hexagon] Be careful about anti-dependencies with a call in packetizerKrzysztof Parzyszek2016-05-061-2/+24
| | | | | | | | | | | In a case like J2_callr <ga:@foo>, %R0<imp-use>, ... R0<def> = ... the anti-dependency on R0 cannot be ignored and the two instructions cannot be packetized together, since if they were, the assignment to R0 would take place before the call. llvm-svn: 268776
* [X86] Get rid of X32_NOREX_ADDR_ACCESS register class.Quentin Colombet2016-05-062-4/+1
| | | | | | | According to H.J. Lu <hjl.tools@gmail.com>, this register class is never used. llvm-svn: 268771
* [AMDGPU][llvm-mc] Add support for sendmsg(...) syntax.Artem Tamazov2016-05-065-27/+379
| | | | | | | | | | | | | | | | | | | Added support for sendmsg(MSG[, OP[, STREAM_ID]]) syntax in s_sendmsg and s_sendmsghalt instructions. The syntax matches the SP3 assembler/disassembler rules. That is why implicit inputs (like M0 and EXEC) are not printed to disassembly output anymore. sendmsg(...) allows only known message types and attributes, even if literals are used instead of symbolic names. However, raw literal (without "sendmsg") still can be used, and that allows for any 16-bit value. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19596 llvm-svn: 268762
* [X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr.Ahmed Bougacha2016-05-061-0/+47
| | | | | | | | Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268760
* [X86] Remove \brief in FixupBW. NFC.Ahmed Bougacha2016-05-061-13/+11
| | | | llvm-svn: 268754
* [X86] Simplify FixupBW sub_8bit_hi-related logic. NFC.Ahmed Bougacha2016-05-061-17/+12
| | | | | | | | | Instead of passing around sizes and asking for subregs, we can check the subreg indices we care about: sub_8bit_hi and sub_8bit. Differential Revision: http://reviews.llvm.org/D20006 llvm-svn: 268753
* [AArch64] Combine callee-save and local stack SP adjustment instructions.Geoff Berry2016-05-063-80/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: If a function needs to allocate both callee-save stack memory and local stack memory, we currently decrement/increment the SP in two steps: first for the callee-save area, and then for the local stack area. This changes the code to allocate them both at once at the very beginning/end of the function. This has two benefits: 1) there is one fewer sub/add micro-op in the prologue/epilogue 2) the stack adjustment instructions act as a scheduling barrier, so moving them to the very beginning/end of the function increases post-RA scheduler's ability to move instructions (that only depend on argument registers) before any of the callee-save stores This change can cause an increase in instructions if the original local stack SP decrement could be folded into the first store to the stack. This occurs when the first local stack store is to stack offset 0. In this case we are trading off one more sub instruction for one fewer sub micro-op (along with benefits (2) and (3) above). Reviewers: t.p.northover Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18619 llvm-svn: 268746
* [AArch64] Decouple zero store promotion from narrow ld merge. NFC.Jun Bum Lim2016-05-061-28/+16
| | | | | | | | | | | | Summary: This change refactors to decouple the zero store promotion from the narrow ld merge and add a flag (enable-narrow-ld-merge=true) to control the narrow ld merge optimization. Reviewers: jmolloy, t.p.northover, mcrosier Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D19885 llvm-svn: 268744
* Revert "AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2."Nikolay Haustov2016-05-062-9/+5
| | | | | | | | This reverts commit 47486d52454d60cdf6becc0b2efe533c73794380. It broke calling OpenCL kernel from another kernel. llvm-svn: 268739
* [mips] Fix inconsistent .cprestore behaviour between direct object emission ↵Daniel Sanders2016-05-063-7/+26
| | | | | | | | | | | | | | | | | | | and assembling. Summary: Direct object emission has an initialization order problem where an InitMCObjectFile is called after MipsTargetELFStreamer determines whether PIC is enabled by default or not. There doesn't seem to be point that initializes all cases so split the responsibility between MipsTargetELFStreamer and MipsAsmPrinter. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19728 llvm-svn: 268737
* [mips] Correct the ordering of HI/LO pairs in the relocation table.Daniel Sanders2016-05-061-186/+269
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: There seems to have been a misunderstanding as to the meaning of 'offset' in the rules laid down by our ABI. The previous code believed that 'offset' meant the offset within the section that the relocation is applied to. However, it should have meant the offset from the symbol used in the relocation expression. This patch adds two fields to ELFRelocationEntry and uses them to correct the order of relocations for MIPS. These fields contain: * The original symbol before shouldRelocateWithSymbol() is considered. This ensures that R_MIPS_GOT16 is able to correctly distinguish between local and external symbols, allowing us to tell whether %got() requires a matching %lo() or not (local symbols require one, external symbols don't). It also prevents confusing cases where the fuzzy matching rules cause things like %hi(foo)/%lo(foo+3) and %hi(bar)/%lo(bar+1) to swap their %lo()'s. * The original offset before shouldRelocateWithSymbol() is considered. The existing Addend field is always zero when the object uses in place addends (because it's already moved it to the encoding) but MIPS needs to use the original offset to ensure that the linker correctly calculates the carry-in bit for %hi() and %got(). IAS ensures that unmatchable %hi()/%got() relocations are placed at the end of the table to ensure that the linker rejects the table (we're unable to report such errors directly). The alternatives to this risk accidental matching against inappropriate relocations which may silently compute incorrect values due to an incorrect carry bit between the %lo() and %hi()/%got(). Reviewers: sdardis Subscribers: dsanders, sdardis, rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D19718 llvm-svn: 268733
* [mips][mips16] Use isUnconditionalBranch() in AnalyzeBranch() and constant ↵Daniel Sanders2016-05-062-14/+4
| | | | | | | | | | | | | | | | island pass. Summary: This stops it misidentifying unconditional branches as conditional branches which fixes a -verify-machineinstrs error about exiting a function via fall through. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19864 llvm-svn: 268731
* [mips][fastisel] Conditional moves do not have implicit operands.Daniel Sanders2016-05-061-5/+4
| | | | | | | | | | Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19862 llvm-svn: 268730
* [TableGen] AsmMatcher: support for default values for optional operandsSam Kolton2016-05-064-106/+118
| | | | | | | | | | | | | | Summary: This change allows to specify "DefaultMethod" for optional operand (IsOptional = 1) in AsmOperandClass that return default value for operand. This is used in convertToMCInst to set default values in MCInst. Previously if you wanted to set default value for operand you had to create custom converter method. With this change it is possible to use standard converters even when optional operands presented. Reviewers: tstellarAMD, ab, craig.topper Subscribers: jyknight, dsanders, arsenm, nhaustov, llvm-commits Differential Revision: http://reviews.llvm.org/D18242 llvm-svn: 268726
* [AVR] Add a majority of the backend codeDylan McKay2016-05-0613-1/+1483
| | | | | | | | | | | | Summary: This adds the majority of the AVR backend. Reviewers: hfinkel, dsanders, vkalintiris, arsenm Subscribers: dylanmckay Differential Revision: http://reviews.llvm.org/D17906 llvm-svn: 268722
* AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2.Nikolay Haustov2016-05-062-5/+9
| | | | | | | | | | | | | | | | | Summary: Check calling convention in AMDGPUMachineFunction::isKernel This will be used for AMDGPU_HSA_KERNEL symbol type in output ELF. Also, in the future unused non-kernels may be optimized. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D19917 llvm-svn: 268719
* [mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructionsZlatko Buljan2016-05-065-20/+52
| | | | | | Differential Revision: http://reviews.llvm.org/D15744 llvm-svn: 268714
* SDAG: Rename Select->SelectImpl and repurpose Select as returning voidJustin Bogner2016-05-0517-40/+39
| | | | | | | | | | | | | | This is a step towards removing the rampant undefined behaviour in SelectionDAG, which is a part of llvm.org/PR26808. We rename SelectionDAGISel::Select to SelectImpl and update targets to match, and then change Select to return void and consolidate the sketchy behaviour we're trying to get away from there. Next, we'll update backends to implement `void Select(...)` instead of SelectImpl and eventually drop the base Select implementation. llvm-svn: 268693
* [scan-build] fix warnings emitted on LLVM Hexagon code baseKrzysztof Parzyszek2016-05-053-1/+3
| | | | | | | | Patch by Apelete Seketeli. Differential Revision: http://reviews.llvm.org/D19968 llvm-svn: 268691
* [Hexagon] Fix the offset ranges for vector memory instructionsKrzysztof Parzyszek2016-05-051-8/+8
| | | | llvm-svn: 268690
* [AArch64] Remove unused MBP headers/dependency. NFC.Chad Rosier2016-05-051-3/+0
| | | | llvm-svn: 268682
* [WebAssembly] Don't emit epilogue code in the middle of stackified code.Dan Gohman2016-05-052-1/+10
| | | | llvm-svn: 268679
* AMDGPU: Simplify control flow / conditionsMatt Arsenault2016-05-051-19/+19
| | | | llvm-svn: 268676
* Touch Hexagon/CMakeLists.txt to regenerate build files, since r268641 ↵NAKAMURA Takumi2016-05-051-1/+1
| | | | | | | complains of missing HexagonAlias.td on ninja. FIXME: TableGen.cmake globs *.td(s) with wildcards for deps. It is not good. llvm-svn: 268666
* ARM: don't attempt to merge litpools referencing different PC-anchors.Tim Northover2016-05-051-3/+3
| | | | | | | | | | | | | | | | | | | | | | Given something like: ldr r0, .LCPI0_0 (== pc-rel var) add r0, pc ldr r1, .LCPI0_1 (== pc-rel var) add r1, pc we cannot combine the 2 ldr instructions and litpools because they get added to a different pc to form the correct address. I think the original logic came from a time when we fused the LDRpci/PICADD instructions into one pseudo-instruction so the PC was always immediately at-hand. That's no longer the case. Should fix general-dynamic TLS access on Linux, and quite possibly other -fPIC code that relies on litpools (e.g. v6m and -Oz compilations) though trivial tweaks of the .ll test didn't provoke anything. llvm-svn: 268662
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