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* [X86] SimplifyDemandedVectorEltsForTargetNode - remove identity target ↵Simon Pilgrim2018-09-291-18/+18
| | | | | | | | shuffles before simplifying inputs By removing demanded target shuffles that simplify to zero/undef/identity before simplifying its inputs we improve chances of further simplification, as only the immediate parent user of the combined is added back to the work list - this still doesn't help us if its passed through other ops though (bitcasts....). llvm-svn: 343390
* [X86][SSE] LowerScalarImmediateShift - remove 32-bit vXi64 special case ↵Simon Pilgrim2018-09-291-129/+65
| | | | | | | | handling. This is all handled generally by getTargetConstantBitsFromNode now llvm-svn: 343387
* Fix signed/unsigned mismatch warning. NFCI.Simon Pilgrim2018-09-291-1/+1
| | | | llvm-svn: 343385
* [X86] getTargetConstantBitsFromNode - add support for rearranging constant ↵Simon Pilgrim2018-09-291-0/+47
| | | | | | | | bits via shuffles Exposed an issue that recursive calls to getTargetConstantBitsFromNode don't handle changes to EltSizeInBits yet. llvm-svn: 343384
* [X86][SSE] LowerScalarImmediateShift - use getTargetConstantBitsFromNode to ↵Simon Pilgrim2018-09-291-64/+74
| | | | | | | | | | get immediate data Don't just attempt to find a splat build vector. First step towards getting rid of all the 32-bit special case code. llvm-svn: 343383
* [X86] getTargetConstantBitsFromNode - fix self-move assertions from gcc ↵Simon Pilgrim2018-09-291-2/+6
| | | | | | builds due to rL343375 llvm-svn: 343377
* [X86] getTargetConstantBitsFromNode - add support for peeking through ↵Simon Pilgrim2018-09-291-0/+15
| | | | | | ISD::EXTRACT_SUBVECTOR llvm-svn: 343375
* [X86][SSE] Fixed issue with v2i64 variable shifts on 32-bit targetsSimon Pilgrim2018-09-291-4/+3
| | | | | | The shift amount might have peeked through a extract_subvector, altering the number of vector elements in the 'Amt' variable - so we were incorrectly calculating the ratio when peeking through bitcasts, resulting in incorrectly detecting splats. llvm-svn: 343373
* [cxx2a] Fix warning triggered by r343285Vitaly Buka2018-09-291-1/+0
| | | | llvm-svn: 343369
* [ARM] Fix correctness checks in promoteToConstantPool.Eli Friedman2018-09-281-46/+15
| | | | | | | | | | | | | | | | | Correctly check for relocations in the constant to promote. And don't allow promoting a constant multiple times. This partially fixes https://bugs.llvm.org//show_bug.cgi?id=32780 ; it's not a complete fix because we also need to prevent ARMConstantIslands from cloning the constant. (-arm-promote-constant is currently off by default, and it stays off with this patch. I'll look into turning it on again when all the known issues are fixed.) Differential Revision: https://reviews.llvm.org/D51472 llvm-svn: 343361
* [ARM] Use preferred alignment for constants in promoteToConstantPool.Eli Friedman2018-09-281-1/+1
| | | | | | | | | | | | | | | This mostly affects IR generated by non-clang frontends because clang generally sets the alignment of globals explicitly. Fixes https://bugs.llvm.org//show_bug.cgi?id=32394 . (-arm-promote-constant is currently off by default, and it stays off with this patch. I'll look into turning it on again when all the known issues are fixed.) Differential Revision: https://reviews.llvm.org/D51469 llvm-svn: 343359
* [AArch64] Split zero cycle feature more granularlyEvandro Menezes2018-09-284-12/+20
| | | | | | | | | | Split the `zcz` feature into specific ones got GP and FP registers, `zcz-gp` and `zcz-fp`, respectively, while retaining the original feature option to mean both. Differential revision: https://reviews.llvm.org/D52621 llvm-svn: 343354
* Revert r343317Luke Cheeseman2018-09-282-16/+0
| | | | | | - asan buildbots are breaking and I need to investigate the issue llvm-svn: 343341
* [X86][Btver2] PSUBS/PSUBUS instructions are zero-idiomsSimon Pilgrim2018-09-281-0/+9
| | | | | | Noticed during llvm-exegesis tests, the PSUBS/PSUBUS instructions have the same zero-idiom behaviour to PSUB llvm-svn: 343321
* Reapply changes reverted by r343235Luke Cheeseman2018-09-282-0/+16
| | | | | | | | - Add fix so that all code paths that create DWARFContext with an ObjectFile initialise the target architecture in the context - Add an assert that the Arch is known in the Dwarf CallFrameString method llvm-svn: 343317
* [MIPS GlobalISel] Lower i64 argumentsPetar Jovanovic2018-09-282-61/+110
| | | | | | | | | | | | | Lower integer arguments larger then 32 bits for MIPS32. setMostSignificantFirst is used in order for G_UNMERGE_VALUES and G_MERGE_VALUES to always hold registers in same order, regardless of endianness. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D52409 llvm-svn: 343315
* [X86][Btver2] CVTSS2I/CVTSD2I - add missing JFPU0 pipeSimon Pilgrim2018-09-281-2/+2
| | | | | | | | We issue JFPU1->JSTC then JFPU0->JFPA then -> JALU0 (integer pipe) Match AMD Fam16h SOG + llvm-exegesis tests llvm-svn: 343314
* [X86][Btver2] Fix BSF/BSR scheduleSimon Pilgrim2018-09-281-2/+2
| | | | | | | | Double throughput to account for 2 pipes + fix BSF's latency/uop counts Match AMD Fam16h SOG + llvm-exegesis tests llvm-svn: 343311
* [ARM] Allow execute only code on Cortex-m23David Spickett2018-09-281-2/+4
| | | | | | | | | | | The NoMovt feature prevents the use of MOVW/MOVT instructions on Cortex-M23 for performance reasons. These instructions are required for execute only code so NoMovt should be disabled when that option is enabled. Differential Revision: https://reviews.llvm.org/D52551 llvm-svn: 343302
* Remove extra whitespace. NFC. (test commit)David Spickett2018-09-281-1/+1
| | | | llvm-svn: 343301
* [ARM][v8.5A] Add speculation barriers SSBB and PSSBBOliver Stannard2018-09-284-1/+45
| | | | | | | | | | | This adds two new barrier instructions which can be used to restrict speculative execution of load instructions. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52484 llvm-svn: 343300
* [X86][BtVer2] Fix PHMINPOS schedule resources typoSimon Pilgrim2018-09-281-1/+1
| | | | | | PHMINPOS can run on either JFPU pipe llvm-svn: 343299
* WebAssembly: Rename GetSignature to GetLibcallSignature [NFC]Derek Schuff2018-09-273-16/+19
| | | | llvm-svn: 343275
* AMDGPU: Split HasExt into HasExtDPP/SDWA/SDWA9Konstantin Zhuravlyov2018-09-274-21/+43
| | | | llvm-svn: 343264
* AMDGPU: Split VOP2Inst into VOP2Inst_e32/e64/sdwaKonstantin Zhuravlyov2018-09-271-10/+32
| | | | llvm-svn: 343259
* AMDGPU/NFC: Simplify VOP_MAC_F16/F32Konstantin Zhuravlyov2018-09-271-11/+2
| | | | llvm-svn: 343254
* [AMDGPU] Fold copy (copy vgpr)Stanislav Mekhanoshin2018-09-271-0/+14
| | | | | | | | This allows to reduce a number of used VGPRs in some cases. Differential Revision: https://reviews.llvm.org/D52577 llvm-svn: 343249
* [X86] Remove BT/BTC/BTR/BTS rr/ri overridesSimon Pilgrim2018-09-271-4/+3
| | | | llvm-svn: 343241
* [X86][Btver2] (V)MPSADBW instructions take 3uops not 1Simon Pilgrim2018-09-271-1/+1
| | | | llvm-svn: 343238
* Revert r343192 as an ubsan build is currently failingLuke Cheeseman2018-09-272-16/+0
| | | | llvm-svn: 343235
* [X86][Btver2] BTC/BTR/BTS instructions take 2uops not 1Simon Pilgrim2018-09-271-1/+1
| | | | llvm-svn: 343234
* [X86] Split BT and BTC/BTR/BTS scheduler classesSimon Pilgrim2018-09-2711-28/+33
| | | | llvm-svn: 343233
* [Sparc] EXPENSIVE_CHECKS now passes all machine verifier errors (PR27461)Simon Pilgrim2018-09-271-4/+0
| | | | | | | | Now that D51487 has landed, the last machine verifier tests that failed EXPENSIVE_CHECKS builds have now been fixed/removed, so we can remove @MatzeB 's isMachineVerifierClean() hack for sparc targets. Differential Revision: https://reviews.llvm.org/D52612 llvm-svn: 343232
* [AArch64] Refactor immediate details out of add/sub tblgen class (NFCI)Oliver Stannard2018-09-271-13/+19
| | | | | | | | | | | | | | Bits [23-22] are used in Add and Sub to specify the shift. The value of the shift field must be 0x; values of 1x are unallocated. MTE adds some instructions that use such encodings, and this patch refactors the Add/Sub class so that another class could derive from this one to implement other encodings and other formats of bitfields. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52489 llvm-svn: 343231
* [AArch64][v8.5A] Add speculation barriers SSBB and PSSBBOliver Stannard2018-09-271-0/+2
| | | | | | | | | | | This adds two new barrier instructions which can be used to restrict speculative execution of load instructions. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52483 llvm-svn: 343229
* [X86][Btver2] BLSI/BLSMSK/BLSR instructions take 2uops not 1 (same as TZCNT)Simon Pilgrim2018-09-271-1/+1
| | | | llvm-svn: 343227
* [AArch64][v8.5A] Add Branch Target Identification instructionsOliver Stannard2018-09-2710-1/+139
| | | | | | | | | | | | This adds new instructions used by the Branch Target Identification feature. When this is enabled, these are the only instructions which can be targeted by indirect branch instructions. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52485 llvm-svn: 343225
* [AArch64][v8.5A] Add speculation restriction system registersOliver Stannard2018-09-276-5/+32
| | | | | | | | | | | This adds some new system registers which can be used to restrict certain types of speculative execution. Patch by Pablo Barrio and David Spickett! Differential revision: https://reviews.llvm.org/D52482 llvm-svn: 343218
* [AArch64][v8.5A] Add Armv8.5-A random number instructionsOliver Stannard2018-09-273-0/+12
| | | | | | | | | | | | | This adds two new system registers, used to generate random numbers. This is an optional extension to v8.5-A, and will be controlled by the "+rng" modifier of the -march= and -mcpu= options. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52481 llvm-svn: 343217
* [AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instructionOliver Stannard2018-09-276-2/+13
| | | | | | | | | | | This adds a new variant of the DC system instruction for persistent memory. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52480 llvm-svn: 343216
* [AArch64][v8.5A] Add prediction invalidation instructions to AArch64Oliver Stannard2018-09-278-4/+89
| | | | | | | | | | | | This adds new system instructions which act as barriers to speculative execution based on earlier execution within a particular execution context. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52479 llvm-svn: 343214
* [ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction setsOliver Stannard2018-09-275-2/+32
| | | | | | | | | | | This is a new barrier which limits speculative execution of the instructions following it. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52477 llvm-svn: 343213
* [AArch64][v8.5A] Add speculation barrier to AArch64 instruction setOliver Stannard2018-09-273-2/+17
| | | | | | | | | | | This is a new barrier which limits speculative execution of the instructions following it. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52476 llvm-svn: 343211
* [Sparc] Remove the support for builtin setjmp/longjmpDaniel Cederman2018-09-273-270/+0
| | | | | | | | | | | | | | | | Summary: It is currently broken and for Sparc there is not much benefit in using a builtin version compared to a library version. Both versions needs to store the same four values in setjmp and flush the register windows in longjmp. If the need for a builtin setjmp/longjmp arises there is an improved implementation available at https://reviews.llvm.org/D50969. Reviewers: jyknight, joerg, venkatra Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D51487 llvm-svn: 343210
* [AArch64][v8.5A] Add FRINT[32,64][Z,X] instructionsOliver Stannard2018-09-274-3/+63
| | | | | | | | | | | | These are some new variants of the "Floating-point Round to Integral" family of instructions, which round to the nearest floating-point value which fits in a 32- or 64-bit integer. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52475 llvm-svn: 343209
* [Sparc] Add unimp aliasDaniel Cederman2018-09-271-0/+3
| | | | | | | | | | | | | Summary: Use 0 as the default immediate for the UNIMP instruction. This matches the behavior in gas. Reviewers: jyknight, venkatra Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D51526 llvm-svn: 343203
* [Sparc] Add support for the partial write PSR instructionDaniel Cederman2018-09-275-1/+26
| | | | | | | | | | | | | | | Summary: Partial write %PSR (WRPSR) is a SPARC V8e option that allows WRPSR instructions to only affect the %PSR.ET field. It is supported by the GR740 and GR716. Reviewers: jyknight, venkatra Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48644 llvm-svn: 343202
* [X86][Btver2] TZCNT instructions take 2uops not 1Simon Pilgrim2018-09-271-1/+1
| | | | llvm-svn: 343200
* [PowerPC] [NFC] Refactor code for printing register operandsNemanja Ivanovic2018-09-276-77/+72
| | | | | | | | | | | | | | | | | | | | | | | We have an unfortunate situation in our back end where we have to keep pairs of functions synchronized. Needless to say that this is not an ideal situation as it is very difficult to enforce. Even without bugs, it's annoying to have to do the same thing in two places. This patch just refactors the code so that the two pairs of those functions that pertain to printing register operands are unified: - stripRegisterPrefix() - this just removes the letter prefixes from registers for the InstrPrinter and AsmPrinter. This patch provides this as a static member of PPCRegisterInfo - Handling of PPCII::UseVSXReg - there are 3 places where we do something special for instructions with that flag set. Each of those places does its own checking of this flag and implements code customization. Any changes to how we print/encode VSX/VMX registers require modifying all 3 places. This patch unifies this into a static function in PPCInstrInfo that returns the register number adjusted as needed. Differential revision: https://reviews.llvm.org/D52467 llvm-svn: 343195
* [X86][Btver2] Add uops counter for exegesis reportsSimon Pilgrim2018-09-271-0/+1
| | | | llvm-svn: 343194
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