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* Several fixes and enhancements to the PPC32 backend.Nate Begeman2004-10-073-147/+154
| | | | | | | | | | | | | | | | | | | | | | 1. Fix an illegal argument to getClassB when deciding whether or not to sign extend a byte load. 2. Initial addition of isLoad and isStore flags to the instruction .td file for eventual use in a scheduler. 3. Rewrite of how constants are handled in emitSimpleBinaryOperation so that we can emit the PowerPC shifted immediate instructions far more often. This allows us to emit the following code: int foo(int x) { return x | 0x00F0000; } _foo: .LBB_foo_0: ; entry ; IMPLICIT_DEF oris r3, r3, 15 blr llvm-svn: 16826
* Add ori reg, reg, 0 as a move instruction. This can be generated fromNate Begeman2004-10-071-0/+11
| | | | | | | | | | | | | | | | | loading a 32bit constant into a register whose low halfword is all zeroes. We now omit the ori after the lis for the following C code: int bar(int y) { return y * 0x00F0000; } _bar: .LBB_bar_0: ; entry ; IMPLICIT_DEF lis r2, 15 mullw r3, r3, r2 blr llvm-svn: 16825
* Remove unnecessary header includeNate Begeman2004-10-071-1/+0
| | | | llvm-svn: 16824
* Correct some typeosChris Lattner2004-10-061-3/+3
| | | | llvm-svn: 16770
* Remove debugging code, fix encoding problem. This fixes the problemsChris Lattner2004-10-062-3/+2
| | | | | | the JIT had last night. llvm-svn: 16766
* Turning on fsel code gen now that we can do so would be good.Nate Begeman2004-10-061-11/+10
| | | | llvm-svn: 16765
* Implement floating point select for lt, gt, le, ge using the powerpc fselNate Begeman2004-10-061-25/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instruction. Now, rather than emitting the following loop out of bisect: .LBB_main_19: ; no_exit.0.i rlwinm r3, r2, 3, 0, 28 lfdx f1, r3, r27 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3) fsub f2, f2, f1 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3) fcmpu cr0, f1, f4 bge .LBB_main_64 ; no_exit.0.i .LBB_main_63: ; no_exit.0.i b .LBB_main_65 ; no_exit.0.i .LBB_main_64: ; no_exit.0.i fmr f2, f1 .LBB_main_65: ; no_exit.0.i addi r3, r2, 1 rlwinm r3, r3, 3, 0, 28 lfdx f1, r3, r27 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3) fsub f4, f4, f1 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f5, lo16(.CPI_main_1-"L00000$pb")(r3) fcmpu cr0, f1, f5 bge .LBB_main_67 ; no_exit.0.i .LBB_main_66: ; no_exit.0.i b .LBB_main_68 ; no_exit.0.i .LBB_main_67: ; no_exit.0.i fmr f4, f1 .LBB_main_68: ; no_exit.0.i fadd f1, f2, f4 addis r3, r30, ha16(.CPI_main_2-"L00000$pb") lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3) fmul f1, f1, f2 rlwinm r3, r2, 3, 0, 28 lfdx f2, r3, r28 fadd f4, f2, f1 fcmpu cr0, f4, f0 bgt .LBB_main_70 ; no_exit.0.i .LBB_main_69: ; no_exit.0.i b .LBB_main_71 ; no_exit.0.i .LBB_main_70: ; no_exit.0.i fmr f0, f4 .LBB_main_71: ; no_exit.0.i fsub f1, f2, f1 addi r2, r2, -1 fcmpu cr0, f1, f3 blt .LBB_main_73 ; no_exit.0.i .LBB_main_72: ; no_exit.0.i b .LBB_main_74 ; no_exit.0.i .LBB_main_73: ; no_exit.0.i fmr f3, f1 .LBB_main_74: ; no_exit.0.i cmpwi cr0, r2, -1 fmr f16, f0 fmr f17, f3 bgt .LBB_main_19 ; no_exit.0.i We emit this instead: .LBB_main_19: ; no_exit.0.i rlwinm r3, r2, 3, 0, 28 lfdx f1, r3, r27 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3) fsub f2, f2, f1 fsel f1, f1, f1, f2 addi r3, r2, 1 rlwinm r3, r3, 3, 0, 28 lfdx f2, r3, r27 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3) fsub f4, f4, f2 fsel f2, f2, f2, f4 fadd f1, f1, f2 addis r3, r30, ha16(.CPI_main_2-"L00000$pb") lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3) fmul f1, f1, f2 rlwinm r3, r2, 3, 0, 28 lfdx f2, r3, r28 fadd f4, f2, f1 fsub f5, f0, f4 fsel f0, f5, f0, f4 fsub f1, f2, f1 addi r2, r2, -1 fsub f2, f1, f3 fsel f3, f2, f3, f1 cmpwi cr0, r2, -1 fmr f16, f0 fmr f17, f3 bgt .LBB_main_19 ; no_exit.0.i llvm-svn: 16764
* Codegen signed mod by 2 or -2 more efficiently. Instead of generating:Chris Lattner2004-10-061-3/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | t: mov %EDX, DWORD PTR [%ESP + 4] mov %ECX, 2 mov %EAX, %EDX sar %EDX, 31 idiv %ECX mov %EAX, %EDX ret Generate: t: mov %ECX, DWORD PTR [%ESP + 4] *** mov %EAX, %ECX cdq and %ECX, 1 xor %ECX, %EDX sub %ECX, %EDX *** mov %EAX, %ECX ret Note that the two marked moves are redundant, and should be eliminated by the register allocator, but aren't. Compare this to GCC, which generates: t: mov %eax, DWORD PTR [%esp+4] mov %edx, %eax shr %edx, 31 lea %ecx, [%edx+%eax] and %ecx, -2 sub %eax, %ecx ret or ICC 8.0, which generates: t: movl 4(%esp), %ecx #3.5 movl $-2147483647, %eax #3.25 imull %ecx #3.25 movl %ecx, %eax #3.25 sarl $31, %eax #3.25 addl %ecx, %edx #3.25 subl %edx, %eax #3.25 addl %eax, %eax #3.25 negl %eax #3.25 subl %eax, %ecx #3.25 movl %ecx, %eax #3.25 ret #3.25 We would be in great shape if not for the moves. llvm-svn: 16763
* Really fix FreeBSD, which apparently doesn't tolerate the extern.Chris Lattner2004-10-061-2/+3
| | | | | | Thanks to Jeff Cohen for pointing out my goof. llvm-svn: 16762
* Fix a scary bug with signed division by a power of two. We used to generate:Chris Lattner2004-10-061-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | s: ;; X / 4 mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, %EAX sar %ECX, 1 shr %ECX, 30 mov %EDX, %EAX add %EDX, %ECX sar %EAX, 2 ret When we really meant: s: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, %EAX sar %ECX, 1 shr %ECX, 30 add %EAX, %ECX sar %EAX, 2 ret Hey, this also reduces register pressure too :) llvm-svn: 16761
* Codegen signed divides by 2 and -2 more efficiently. In particularChris Lattner2004-10-061-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instead of: s: ;; X / 2 movl 4(%esp), %eax movl %eax, %ecx shrl $31, %ecx movl %eax, %edx addl %ecx, %edx sarl $1, %eax ret t: ;; X / -2 movl 4(%esp), %eax movl %eax, %ecx shrl $31, %ecx movl %eax, %edx addl %ecx, %edx sarl $1, %eax negl %eax ret Emit: s: movl 4(%esp), %eax cmpl $-2147483648, %eax sbbl $-1, %eax sarl $1, %eax ret t: movl 4(%esp), %eax cmpl $-2147483648, %eax sbbl $-1, %eax sarl $1, %eax negl %eax ret llvm-svn: 16760
* Add some new instructions. Fix the asm string for sbb32rrChris Lattner2004-10-063-3/+24
| | | | llvm-svn: 16759
* FreeBSD uses GCC. Patch contributed by Jeff Cohen!Chris Lattner2004-10-061-3/+2
| | | | llvm-svn: 16756
* * Prune #includesChris Lattner2004-10-041-101/+27
| | | | | | | | * Update comments * Rearrange code a bit * Finally ELIMINATE the GAS workaround emitter for Intel mode. woot! llvm-svn: 16647
* Add support for emitting AT&T style .s files, and make it the default. UsersChris Lattner2004-10-041-128/+307
| | | | | | may now choose their output format with the -x86-asm-syntax={intel|att} flag. llvm-svn: 16646
* Convert some missed patterns to support AT&T styleChris Lattner2004-10-041-8/+8
| | | | llvm-svn: 16645
* Apparently the GNU assembler has a HUGE hack to be compatible with reallyChris Lattner2004-10-041-9/+12
| | | | | | | | | old and broken AT&T syntax assemblers. The problem with this hack is that *SOME* forms of the fdiv and fsub instructions have the 'r' bit inverted. This was a real pain to figure out, but is trivially easy to support: thus we are now bug compatible with gas and gcc. llvm-svn: 16644
* Fix incorrect suffixChris Lattner2004-10-041-1/+1
| | | | llvm-svn: 16642
* Fix some more missed suffixes and swapped operandsChris Lattner2004-10-041-34/+40
| | | | llvm-svn: 16641
* Add missing suffixes to FP instructions for AT&T modeChris Lattner2004-10-041-38/+33
| | | | llvm-svn: 16640
* Add support for the -x86-asm-syntax flag, which can be used to choose betweenChris Lattner2004-10-033-14/+48
| | | | | | | | Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. llvm-svn: 16639
* Add support to the instruction patterns for AT&T style output, which willChris Lattner2004-10-031-569/+963
| | | | | | | | | hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. llvm-svn: 16638
* Add initial support for variantsChris Lattner2004-10-031-2/+10
| | | | llvm-svn: 16635
* Make EmitMappingInfo into an "external location" option, so that it can be setBrian Gaeke2004-09-301-1/+7
| | | | | | or cleared externally. llvm-svn: 16623
* I think this will handle double args.Brian Gaeke2004-09-301-2/+15
| | | | llvm-svn: 16618
* Mark the instructions that have delay slots with the hasDelaySlot flag.Brian Gaeke2004-09-301-9/+17
| | | | | | Add some comments. llvm-svn: 16611
* Use TargetMachine::hasDelaySlot() instead of our old switch statementBrian Gaeke2004-09-301-45/+6
| | | | | | to find instrs that have delay slots. llvm-svn: 16610
* Change the #ifdefs to allow compilation with a V8 compiler, but the JIT stillMisha Brukman2004-09-292-6/+6
| | | | | | | won't work if not compiled in V9 mode, currently by GCC only, because Sun's system compiler does not tell us if it's a V8 or V9 system. llvm-svn: 16602
* Update list of shootout programs that should be working.Brian Gaeke2004-09-291-2/+2
| | | | llvm-svn: 16595
* Tell the target description that calls clobber registers O0...O5.Brian Gaeke2004-09-291-10/+9
| | | | llvm-svn: 16594
* FITOD is spelled "fitod", not "fitos". Ouch.Brian Gaeke2004-09-291-1/+1
| | | | llvm-svn: 16591
* Don't use .quad to output double constants. The assembler must have a bug orBrian Gaeke2004-09-291-1/+2
| | | | | | something, because the wrong bit patterns get output. llvm-svn: 16590
* Recognize FpMOVD as a move.Brian Gaeke2004-09-291-1/+1
| | | | llvm-svn: 16586
* Generate better code by being far less clever when it comes to the select ↵Nate Begeman2004-09-291-7/+17
| | | | | | instruction. Don't create overlapping register lifetimes llvm-svn: 16580
* add resultsBrian Gaeke2004-09-291-0/+7
| | | | llvm-svn: 16579
* improve Type::BoolTy codegen by eliminating unnecessary clears and sign extendsNate Begeman2004-09-291-1/+8
| | | | llvm-svn: 16578
* Simplify copyConstantToRegister() for longs, using a pair of recursive calls.Brian Gaeke2004-09-291-62/+106
| | | | | | | | | | | | | | Copy constant-pool entries' addresses into registers before loading out of them, to avoid errors from the assembler. Handle loading call args past the 6th one off the stack. Add IMPLICIT_DEF pseudo-instrs for double and long arguments passed in register pairs. Use FpMOVD to copy doubles around instead of the horrible store-load thing we were doing before. Handle 'ret double' and 'ret long'. Fix a bug in handling 'and/or/xor long'. llvm-svn: 16577
* Fix bug recognizing moves: isMoveInstr should only treat ORs with %g0 asBrian Gaeke2004-09-291-1/+1
| | | | | | moves, not all ORs. llvm-svn: 16576
* Use FpMOVD pseudo-instruction to move doubles around.Brian Gaeke2004-09-291-0/+2
| | | | llvm-svn: 16575
* Add new FpMOVD pseudo-instruction, used to move doubles around.Brian Gaeke2004-09-291-0/+1
| | | | llvm-svn: 16574
* Fix double and long alignment.Brian Gaeke2004-09-291-1/+3
| | | | | | Call the FPMover pass after register allocation. llvm-svn: 16573
* Put quotes around argument to .section directive.Brian Gaeke2004-09-291-3/+3
| | | | llvm-svn: 16572
* Add createSparcV8FPMoverPass().Brian Gaeke2004-09-291-0/+1
| | | | llvm-svn: 16571
* Pass which converts FpMOVD (double move pseudoinstructions) to pairsBrian Gaeke2004-09-291-0/+91
| | | | | | of FMOVS instrs. llvm-svn: 16570
* To go along with sabre's improved InstCombining, improve recognition ofNate Begeman2004-09-291-21/+9
| | | | | | | | | | | | | | | integers that we can use as immediate values in instructions. Example from yacr2: - lis r10, -1 - ori r10, r10, 65535 - add r28, r28, r10 + addi r28, r28, -1 addi r7, r7, 1 addi r9, r9, 1 b .LBB_main_9 ; loopentry.1.i214 llvm-svn: 16566
* Add support for the isLoad and isStore flags, needed by the instruction ↵Nate Begeman2004-09-281-0/+2
| | | | | | scheduler llvm-svn: 16555
* Capture delay slot infoChris Lattner2004-09-281-0/+1
| | | | llvm-svn: 16551
* Since we use alloca now make sure we include the proper headers for it.Alkis Evlogimenos2004-09-281-0/+1
| | | | llvm-svn: 16536
* Use alloca instead of a C99 style array. This should fix theAlkis Evlogimenos2004-09-281-4/+6
| | | | | | compilation problem in windows. llvm-svn: 16535
* Pull assignment out of for loop conditional in order for this toAlkis Evlogimenos2004-09-281-2/+2
| | | | | | compile under windows. Patch contributed by Paolo Invernizzi! llvm-svn: 16534
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