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* R600/SI: Emit config values in register value pairs.Tom Stellard2013-04-152-3/+38
| | | | | | | | Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. llvm-svn: 179546
* R600/SI: Emit configuration value in the .AMDGPU.config ELF sectionTom Stellard2013-04-151-1/+9
| | | | llvm-svn: 179545
* R600: Emit ELF formatted code rather than raw ISA.Tom Stellard2013-04-155-12/+63
| | | | llvm-svn: 179544
* Mark all PPC comparison instructions as not having side effectsHal Finkel2013-04-152-20/+28
| | | | | | | | | | Now that the CR spilling issues have been resolved, we can remove the unmodeled-side-effect attributes from the comparison instructions (and also mark them as isCompare). By allowing these, by default, to have unmodeled side effects, we were hiding problems with CR spilling; but everything seems much happier now. llvm-svn: 179502
* Fix PPC64 CR spill location for callee-saved registersHal Finkel2013-04-152-35/+50
| | | | | | | | | | | | | | | | This fixes an ABI bug for non-Darwin PPC64. For the callee-saved condition registers, the spill location is specified relative to the stack pointer (SP + 8). However, this is not relative to the SP after the new stack frame is established, but instead relative to the caller's stack pointer (it is stored into the linkage area of the parent's stack frame). So, like with the link register, we don't directly spill the CRs with other callee-saved registers, but just mark them to be spilled during prologue generation. In practice, this reverts r179457 for PPC64 (but leaves it in place for PPC32). llvm-svn: 179500
* Use i32 for all SPARC shift amounts, even in 64-bit mode.Jakob Stoklund Olesen2013-04-144-7/+8
| | | | | | Test case by llvm-stress. llvm-svn: 179477
* Add support for the abs64 SPARC v9 code model.Jakob Stoklund Olesen2013-04-141-0/+9
| | | | | | For when 16 TB just isn't enough. llvm-svn: 179474
* Add support for the SPARC v9 abs44 code model.Jakob Stoklund Olesen2013-04-141-6/+16
| | | | | | | This is the default model for non-PIC 64-bit code. It supports text+data+bss linked anywhere in the low 16 TB of the address space. llvm-svn: 179473
* Use target flags for printing SPARC asm operands.Jakob Stoklund Olesen2013-04-141-16/+34
| | | | | | | 64-bit code models need multiple relocations that can't be inferred from the opcode like they can in 32-bit code. llvm-svn: 179472
* Also put target flags on SPARC constant pool references.Jakob Stoklund Olesen2013-04-142-26/+36
| | | | | | | Constant pool entries are accessed exactly the same way as global variables. llvm-svn: 179471
* Fix patterns for 64-bit pointers.Jakob Stoklund Olesen2013-04-141-4/+2
| | | | | | This fixes the pic32 code model for SPARC v9. llvm-svn: 179469
* Add target flags to SPARC address operands.Jakob Stoklund Olesen2013-04-143-14/+95
| | | | | | | | | SDNodes and MachineOperands get target flags representing the %hi() and %lo() assembly annotations that eventually become relocations. Also define flags to be used by the 64-bit code models. llvm-svn: 179468
* Mark all PPC CR registers to be spilled as live-in and tag MFCR appropriatelyHal Finkel2013-04-133-15/+16
| | | | | | | | | | | | Leaving MFCR has having unmodeled side effects is not enough to prevent unwanted instruction reordering post-RA. We could probably apply a stronger barrier attribute, but there is a better way: Add all (not just the first) CR to be spilled as live-in to the entry block, and add all CRs to the MFCR instruction as implicitly killed. Unfortunately, I don't have a small test case. llvm-svn: 179465
* Define SPARC code models.Jakob Stoklund Olesen2013-04-132-4/+32
| | | | | | | Currently, only abs32 and pic32 are implemented. Add a test case for abs32 with 64-bit code. 64-bit PIC code is currently broken. llvm-svn: 179463
* Use the correct types when matching ADDRri patterns from frame indexes.Jakob Stoklund Olesen2013-04-131-3/+4
| | | | | | | It doesn't seem like anybody is checking types this late in isel, so no test case. llvm-svn: 179462
* Spill and restore PPC CR registers using the FP when we have oneHal Finkel2013-04-131-6/+14
| | | | | | | | | | For functions that need to spill CRs, and have dynamic stack allocations, the value of the SP during the restore is not what it was during the save, and so we need to use the FP in these cases (as for all of the other spills and restores, but the CR restore has a special code path because its reserved slot, like the link register, is specified directly relative to the adjusted SP). llvm-svn: 179457
* X86 machine model: reduce SandyBridge and Haswell ILPWindow.Andrew Trick2013-04-132-2/+2
| | | | | | | | | | | | | | | The initial values were arbitrary. I want them to be more conservative. This represents the number of latency cycles hidden by OOO execution. In practice, I think it should be within a small factor of the complex floating point operation latency so the scheduler can make some attempt to hide latency even for smallish blocks. These are by no means the best values, just a starting point for tuning heuristics. Some benchmarks such as TSVC run faster with this lower value for SandyBridge. I haven't run anything on Haswell, but it's shouldn't be 2x SB. llvm-svn: 179450
* Catch another case where SD fails to propagate node order.Andrew Trick2013-04-131-1/+4
| | | | | | | | | | I need to handle this for the test case in my following scheduler commit. Work is already under way to redesign the mechanism for node order propagation because this case by case approach is unmaintainable. llvm-svn: 179448
* [mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN andAkira Hatanaka2013-04-134-172/+174
| | | | | | | | lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering. No functionality changes. llvm-svn: 179444
* [mips] Reapply r179420 and r179421.Akira Hatanaka2013-04-134-11/+41
| | | | llvm-svn: 179434
* [mips] Override TargetLoweringBase::isShuffleMaskLegal.Akira Hatanaka2013-04-131-0/+5
| | | | llvm-svn: 179433
* [ms-inline asm] Simplify the logic by using parsePrimaryExpr. No functionalChad Rosier2013-04-121-1/+1
| | | | | | | change intended. Test case previously added in r178568. Part of rdar://13611297 llvm-svn: 179425
* Revert r179420 and r179421.Akira Hatanaka2013-04-124-41/+11
| | | | llvm-svn: 179422
* [mips] Instruction selection patterns for carry-setting and using addAkira Hatanaka2013-04-123-6/+15
| | | | | | instructions. llvm-svn: 179421
* [mips] v4i8 and v2i16 add, sub and mul instruction selection patterns.Akira Hatanaka2013-04-122-5/+26
| | | | llvm-svn: 179420
* [ms-inline asm] Move this logic into a static function as it's only applicableChad Rosier2013-04-121-63/+67
| | | | | | when parsing MS-style inline assembly. No functional change intended. llvm-svn: 179407
* [ms-inline asm] Address the FIXME for ImmDisp before brackets. ThisChad Rosier2013-04-121-18/+29
| | | | | | | | is a follow on to r179393 and r179399. Test case to be added on the clang side. Part of rdar://13453209 llvm-svn: 179403
* [ms-inline asm] Have the [ Symbol ] case fall into the more general logic. ThisChad Rosier2013-04-121-46/+24
| | | | | | | is a follow on to r179393. Test case to be added on the clang side. Part of rdar://13453209 llvm-svn: 179399
* ARM: Correct printing of pre-indexed operands.Quentin Colombet2013-04-124-26/+57
| | | | | | | | | | | | | According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
* [ms-inline asm] Add support for operands that include both a symbol and anChad Rosier2013-04-121-41/+103
| | | | | | | | | immediate displacement. Specifically, add support for generating the proper IR. We've been able to parse this for some time now. Test case to be added on the clang side. Part of rdar://13453209 llvm-svn: 179393
* PPC: Remove (broken) nested implicit definition listsHal Finkel2013-04-122-94/+153
| | | | | | | | | | TableGen will not combine nested list 'let' bindings into a single list, and instead uses only the inner scope. As a result, several instruction definitions were missing implicit register defs that were in outer scopes. This de-nests these scopes and makes all instructions have only one let binding which sets implicit register definitions. llvm-svn: 179392
* Add a comment about the PPC Interpretation64Bit bitHal Finkel2013-04-121-0/+5
| | | | llvm-svn: 179391
* Hexagon: Set isPredicatedNew flag on predicate new instructions.Jyotsna Verma2013-04-122-22/+21
| | | | llvm-svn: 179388
* Hexagon: Set isPredicatedFlase flag for all the instructions with negated ↵Jyotsna Verma2013-04-122-21/+21
| | | | | | predication. llvm-svn: 179387
* Add PPC instruction record forms and associated query functionsHal Finkel2013-04-125-416/+670
| | | | | | | | | | | | | | | | | | This is prep. work for the implementation of optimizeCompare. Many PPC instructions have 'record' forms (in almost all cases, this means that the RC bit is set) that cause the result of the instruction to be compared with zero, and the result of that comparison saved in a predefined condition register. In order to add the record forms of the instructions without too much copy-and-paste, the relevant functions have been refactored into multiclasses which define both the record and normal forms. Also, two TableGen-generated mapping functions have been added which allow querying the instruction code for the record form given the normal form (and vice versa). No functionality change intended. llvm-svn: 179356
* [ms-inline asm] Add support for using the LENGTH, TYPE, and SIZE operators withChad Rosier2013-04-111-2/+11
| | | | | | | | variables that use namespace alias qualifiers. Test case coming on clang side shortly. Part of rdar://13499009 llvm-svn: 179343
* [ms-inline asm] Add support for using offsetof operator with variables that useChad Rosier2013-04-111-3/+6
| | | | | | | namespace alias qualifiers. Test case coming on clang side shortly. Part of rdar://13499009 llvm-svn: 179339
* [ms-inline asm] Pass a StringRef reference to ParseIntelVarWithQualifier so weChad Rosier2013-04-111-15/+15
| | | | | | | | can build up the identifier string. No test case as support for looking up these type of identifiers hasn't been implemented on the clang side. Part of rdar://13499009 llvm-svn: 179336
* [ms-inline asm] Remove brackets from around a symbol reference in the targetChad Rosier2013-04-111-0/+10
| | | | | | | | specific logic. This makes the code much less fragile. Test case coming on the clang side in a moment. rdar://13634327 llvm-svn: 179323
* Fix undefined behavior in AArch64David Majnemer2013-04-111-7/+11
| | | | | | | | A64Imms::isLogicalImmBits and A64Imms::isLogicalImm will attempt to execute shifts that perform undefined behavior. Instead of attempting to perform the 64-bit rotation, treat it as a no-op. llvm-svn: 179317
* [mips] Custom-lower i64 MULHS and MULHU nodes. Remove the code which selectsAkira Hatanaka2013-04-112-64/+4
| | | | | | | | multiply instructions in MipsSEDAGToDAGISel. This patch was supposed to be part of r178403. llvm-svn: 179314
* [mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp.Akira Hatanaka2013-04-113-13/+12
| | | | | | | | | | - Rename function. - Pass iterator by value. - Remove header include. No functionality changes. llvm-svn: 179312
* Optimize vector select from all 0s or all 1sMichael Liao2013-04-111-0/+45
| | | | | | | | As packed comparisons in AVX/SSE produce all 0s or all 1s in each SIMD lane, vector select could be simplified to AND/OR or removed if one or both values being selected is all 0s or all 1s. llvm-svn: 179267
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-115-34/+56
| | | | | | | As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. llvm-svn: 179266
* Enhance bool simplifcation in X86 to handle more casesMichael Liao2013-04-111-6/+35
| | | | | | | | | | | | This patch is revised based on patch from Victor Umansky <victor.umansky@intel.com>. More cases are handled in X86's bool simplification, i.e. - SETCC_CARRY - value is truncated to i1 with AND As a by-product, PR5443 is also fixed. llvm-svn: 179265
* R600ControlFlowFinalizer.cpp: Fix a warning. [-Wunused-variable]NAKAMURA Takumi2013-04-111-0/+1
| | | | llvm-svn: 179263
* Whitespace.NAKAMURA Takumi2013-04-111-2/+1
| | | | llvm-svn: 179262
* Make PPCInstrInfo::isPredicated always return falseHal Finkel2013-04-111-16/+8
| | | | | | | Because of how predication in implemented on PPC (only for branches), I think that this is the right thing to do. No functionality change intended. llvm-svn: 179252
* MC: Support COFF image-relative MCSymbolRefsNico Rieck2013-04-101-2/+16
| | | | | | | | | | | | | | | | Add support for the COFF relocation types IMAGE_REL_I386_DIR32NB and IMAGE_REL_AMD64_ADDR32NB for 32- and 64-bit respectively. These are similar to normal 4-byte relocations except that they do not include the base address of the image. Image-relative relocations are used for debug information (32-bit) and SEH unwind tables (64-bit). A new MCSymbolRef variant called 'VK_COFF_IMGREL32' is introduced to specify such relocations. For AT&T assembly, this variant can be accessed using the symbol suffix '@imgrel'. llvm-svn: 179240
* fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test casesKay Tiong Khoo2013-04-101-3/+3
| | | | llvm-svn: 179223
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