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* Fill delay slot with useful instructions. Modified from Sparc's version of delayAkira Hatanaka2011-09-291-12/+201
| | | | | | | | slot filler. Patch by Reed Kotler at Mips Technologies. llvm-svn: 140825
* Create a machine basic block in the constant pool and retrieve the symbol ↵Bill Wendling2011-09-292-0/+7
| | | | | | for an MBB. llvm-svn: 140824
* Support creating a constant pool value for a machine basic block.Bill Wendling2011-09-292-2/+30
| | | | | | | This is used when we want to take the address of a machine basic block, but it's not associated with a BB in LLVM IR. llvm-svn: 140823
* Mips64 arithmetic and logical instructions with two source registers.Akira Hatanaka2011-09-291-0/+30
| | | | llvm-svn: 140806
* Clean up uses of switch instructions so they are not dependent on the ↵Eli Friedman2011-09-292-11/+21
| | | | | | operand ordering. Patch by Stepan Dyatkovskiy. llvm-svn: 140803
* PTX: Fix broken shared library buildJustin Holewinski2011-09-294-22/+43
| | | | llvm-svn: 140783
* Expand the x86 V_SET0* pseudos right after register allocation.Jakob Stoklund Olesen2011-09-294-60/+66
| | | | | | | This also makes it possible to reduce the number of pseudo instructions and get rid of the encoding information. llvm-svn: 140776
* Target/ARM: Unbreak! CMake! Build!NAKAMURA Takumi2011-09-291-1/+0
| | | | llvm-svn: 140774
* Delete NEONMoveFix, now unused.Jakob Stoklund Olesen2011-09-293-149/+0
| | | | llvm-svn: 140773
* Use ExecutionDepsFix instead of NEONMoveFix.Jakob Stoklund Olesen2011-09-292-11/+21
| | | | | | | This enables NEON domain tracking across basic blocks, but should otherwise do the same thing. llvm-svn: 140772
* Move to ISelLowering.Bill Wendling2011-09-293-131/+0
| | | | llvm-svn: 140754
* PTX: Add new patterns for bitconvert and any_extendJustin Holewinski2011-09-291-213/+208
| | | | llvm-svn: 140753
* Revert r140731, "Define classes for unary and binary FP instructions and use ↵Jakob Stoklund Olesen2011-09-282-63/+55
| | | | | | | | them to define" It broke the unit tests. Please reapply with tests fixed. llvm-svn: 140735
* Tighten a ARM dag combine condition to avoid an identity transformation, whichEvan Cheng2011-09-281-1/+1
| | | | | | | | ends up introducing a cycle in the DAG. rdar://10196296 llvm-svn: 140733
* Define classes for unary and binary FP instructions and use them to defineAkira Hatanaka2011-09-282-55/+63
| | | | | | multiclasses. llvm-svn: 140731
* PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU ↵Eli Friedman2011-09-281-0/+7
| | | | | | does not support them. llvm-svn: 140723
* Perform the lowering only if there are invokes.Bill Wendling2011-09-281-9/+19
| | | | llvm-svn: 140719
* Ahem...actually *add* the ARMSjLjLowering pass to the pass manager.Bill Wendling2011-09-281-1/+1
| | | | llvm-svn: 140718
* PTX: Fix alignment logicJustin Holewinski2011-09-281-1/+1
| | | | llvm-svn: 140709
* Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit.Akira Hatanaka2011-09-281-9/+10
| | | | llvm-svn: 140705
* Remove definitions of branch-on-FP-likely instructions. They are deprecated.Akira Hatanaka2011-09-281-4/+0
| | | | llvm-svn: 140704
* Mips64 predicate definitions. Patch by Liu.Akira Hatanaka2011-09-281-0/+7
| | | | llvm-svn: 140703
* PTX: MC-ize the PTX backend (patch 2 of N)Justin Holewinski2011-09-282-12/+3
| | | | | | Get rid of some of the no-longer-needed parts of PTXAsmPrinter. llvm-svn: 140698
* PTX: MC-ize the PTX back-end (patch 1 of N)Justin Holewinski2011-09-2819-64/+449
| | | | | | | | Lay some groundwork for converting to MC-based asm printer. This is the first of probably many patches to bring the back-end back up-to-date with all of the recent MC changes. llvm-svn: 140697
* Check in a patch that has already been code reviewed by Owen that I'd ↵James Molloy2011-09-288-12/+128
| | | | | | | | | | | | forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. llvm-svn: 140696
* PTX: Simplify code. No functionality change.Benjamin Kramer2011-09-281-13/+5
| | | | llvm-svn: 140680
* PTX: Pass param name strings per const reference.Benjamin Kramer2011-09-282-7/+7
| | | | | | The copies caused use-after-free bugs on std::string implementations without COW (i.e. anything but libstdc++) llvm-svn: 140679
* Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix.Jakob Stoklund Olesen2011-09-282-521/+0
| | | | | | I'll clean up the source in the next commit. llvm-svn: 140663
* Remove MipsFPRound. Mips1 is no longer supported.Akira Hatanaka2011-09-271-4/+0
| | | | llvm-svn: 140661
* Remove X86-dependent stuff from SSEDomainFix.Jakob Stoklund Olesen2011-09-273-21/+31
| | | | | | | | | This also enables domain swizzling for AVX code which required a few trivial test changes. The pass will be moved to lib/CodeGen shortly. llvm-svn: 140659
* Unbreak CMake build.Ted Kremenek2011-09-272-2/+3
| | | | llvm-svn: 140655
* Implement TII::get/setExecutionDomain() for ARM.Jakob Stoklund Olesen2011-09-272-0/+59
| | | | llvm-svn: 140653
* Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo.Jakob Stoklund Olesen2011-09-273-10/+8
| | | | | | | | I am going to unify the SSEDomainFix and NEONMoveFix passes into a single target independent pass. They are essentially doing the same thing. llvm-svn: 140652
* ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.Jim Grosbach2011-09-271-0/+10
| | | | | | | | Add inst alias to handle these assembly forms. Add tests, too. rdar://10178799 llvm-svn: 140647
* This is the start of the new SjLj EH preparation pass, which will replace theBill Wendling2011-09-273-1/+122
| | | | | | | | | | | | | | | | | | | current IR-level pass. The old SjLj EH pass has some problems, especially with the new EH model. Most significantly, it violates some of the new restrictions the new model has. For instance, the 'dispatch' table wants to jump to the landing pad, but we cannot allow that because only an invoke's unwind edge can jump to a landing pad. This requires us to mangle the code something awful. In addition, we need to keep the now dead landingpad instructions around instead of CSE'ing them because the DWARF emitter uses that information (they are dead because no control flow edge will execute them - the control flow edge from an invoke's unwind is superceded by the edge coming from the dispatch). Basically, this pass belongs not at the IR level where SSA is king, but at the code-gen level, where we have more flexibility. llvm-svn: 140646
* Embed patterns in definitions of MFC1 and MTC1 instead of defining them outsideAkira Hatanaka2011-09-271-5/+4
| | | | | | of the instruction definitions using Pat<>. llvm-svn: 140644
* Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().Jim Grosbach2011-09-272-2/+2
| | | | | | Naming conventions consistency. No functional change. llvm-svn: 140636
* PTX: Fix case where printed alignment could be 0Justin Holewinski2011-09-271-1/+1
| | | | llvm-svn: 140624
* PTX: Use external symbols to keep track of params and locals. This also fixesJustin Holewinski2011-09-276-55/+64
| | | | | | | a couple of outstanding issues with frame objects occuring as instruction operands. llvm-svn: 140616
* Use existing function.Jakob Stoklund Olesen2011-09-271-13/+1
| | | | llvm-svn: 140615
* Fix function MipsRegisterInfo::getRegisterNumbering.Akira Hatanaka2011-09-271-33/+81
| | | | | | Return numbers of 64-bit registers. llvm-svn: 140609
* Do not add the pass that restores $gp if target is Mips64.Akira Hatanaka2011-09-271-1/+4
| | | | llvm-svn: 140607
* Mark MipsPseudo isPseudo.Akira Hatanaka2011-09-271-1/+3
| | | | llvm-svn: 140598
* PTX: Add support for sitofp in backendJustin Holewinski2011-09-271-0/+25
| | | | llvm-svn: 140593
* Remove extraneous commit garbage.Owen Anderson2011-09-261-2/+0
| | | | llvm-svn: 140581
* Set register class of a register according to value of HasMips64.Akira Hatanaka2011-09-261-1/+1
| | | | llvm-svn: 140570
* Define variable HasMips64 in MipsTargetLowering.Akira Hatanaka2011-09-262-4/+5
| | | | llvm-svn: 140569
* In single float mode, double precision FP arguments are passed in integerAkira Hatanaka2011-09-261-4/+3
| | | | | | registers, so there is no need to check here. llvm-svn: 140568
* ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.Owen Anderson2011-09-263-3/+37
| | | | llvm-svn: 140560
* PTX: Fix memcpy intrinsic to handle 64-bit pointersJustin Holewinski2011-09-261-8/+9
| | | | llvm-svn: 140556
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