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* [X86][SSE] Improve recognition of uitofp conversions that can be performed ↵Simon Pilgrim2016-09-181-3/+9
| | | | | | | | | | | | | | as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
* [X86][SSE] Improve target shuffle mask extractionSimon Pilgrim2016-09-171-10/+14
| | | | | | Add ability to extract vXi64 'vzext_movl' masks on 32-bit targets llvm-svn: 281834
* [Hexagon] segv while processing SUnit with nullNodePtrRon Lieberman2016-09-171-0/+4
| | | | | | Added BoundaryNode check to isBestZeroLatency function. llvm-svn: 281825
* AMDGPU: Fix broken FrameIndex handlingMatt Arsenault2016-09-175-99/+19
| | | | | | | | | | | | | | | | | We were trying to avoid using a FrameIndex operand in non-pointer operands in a convoluted way, and would break because of using TargetFrameIndex. The TargetFrameIndex should only be used in the case where it makes sense to fold it as part of the addressing mode, otherwise it requires materialization like a normal constant. This wasn't working reliably and failed in the added testcase, hitting the assert when processing the frame index. The TargetFrameIndex was coming from trying to produce an AssertZext limiting the maximum stack size. I'm not sure this was correct to begin with, because it is apparently possible to have a single workitem dispatch that requires all 4G of private memory. llvm-svn: 281824
* AMDGPU: Rename spill operands to match real instructionMatt Arsenault2016-09-172-13/+13
| | | | llvm-svn: 281823
* AMDGPU: Push bitcasts through build_vectorMatt Arsenault2016-09-171-0/+27
| | | | | | | | This reduces the number of copies and reg_sequences when using fp constant vectors. This significantly reduces the code size in local-stack-alloc-bug.ll llvm-svn: 281822
* AMDGPU: Use i64 scalar compare instructionsMatt Arsenault2016-09-174-12/+45
| | | | | | VI added eq/ne for i64, so use them. llvm-svn: 281800
* AMDGPU/SI: Fix kernel argument ABI for HSATom Stellard2016-09-161-1/+2
| | | | | | | | | | | | Summary: i8, i16, and f16 values are not extended to 32-bit in the HSA kernel ABI. Reviewers: arsenm Subscribers: arsenm, kzhuravl, wdng, nhaehnle, llvm-commits, yaxunl Differential Revision: https://reviews.llvm.org/D24621 llvm-svn: 281789
* AMDGPU: Allow some control flow intrinsics to be CSEdMatt Arsenault2016-09-165-27/+80
| | | | | | | | | | | These clean up some unnecessary or instructions in cases with complex loops. In the original testcase I noticed this, the same or with exec was repeated 5 or 6 times in a row. With this only one is emitted or sometimes a copy. llvm-svn: 281786
* AMDGPU: Refactor kernel argument loweringTom Stellard2016-09-164-52/+109
| | | | | | | | | | | | | | | | | | | Summary: The main challenge in lowering kernel arguments for AMDGPU is determing the memory type of the argument. The generic calling convention code assumes that only legal register types can be stored in memory, but this is not the case for AMDGPU. This consolidates all the logic AMDGPU uses for deducing memory types into a single function. This will make it much easier to support different ABIs in the future. Reviewers: arsenm Subscribers: arsenm, wdng, nhaehnle, llvm-commits, yaxunl Differential Revision: https://reviews.llvm.org/D24614 llvm-svn: 281781
* AMDGPU: Use SOPK compare instructionsMatt Arsenault2016-09-167-51/+152
| | | | llvm-svn: 281780
* AMDGPU/SI: Add support for triples with the mesa3d operating systemTom Stellard2016-09-167-13/+22
| | | | | | | | | | | | | | Summary: mesa3d will use the same kernel calling convention as amdhsa, but it will handle everything else like the default 'unknown' OS type. Reviewers: arsenm Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D22783 llvm-svn: 281779
* Defer asm errors to post-statement failureNirav Dave2016-09-167-223/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recommitting after fixing AsmParser initialization and X86 inline asm error cleanup. Allow errors to be deferred and emitted as part of clean up to simplify and shorten Assembly parser code. This will allow error messages to be emitted in helper functions and be modified by the caller which has better context. As part of this many minor cleanups to the Parser: * Unify parser cleanup on error * Add Workaround for incorrect return values in ParseDirective instances * Tighten checks on error-signifying return values for parser functions and fix in-tree TargetParsers to be more consistent with the changes. * Fix AArch64 test cases checking for spurious error messages that are now fixed. These changes should be backwards compatible with current Target Parsers so long as the error status are correctly returned in appropriate functions. Reviewers: rnk, majnemer Subscribers: aemerson, jyknight, llvm-commits Differential Revision: https://reviews.llvm.org/D24047 llvm-svn: 281762
* Actually remove the Mangler from the AsmPrinter and clean up the places it ↵Eric Christopher2016-09-167-15/+7
| | | | | | was "used" but not used. llvm-svn: 281749
* Fix a hidden use of grabbing the Mangler from the AsmPrinter and updateEric Christopher2016-09-161-4/+4
| | | | | | accordingly. llvm-svn: 281748
* [AArch64][GlobalISel] Add default regbank mapping for int<>FP.Ahmed Bougacha2016-09-161-0/+10
| | | | llvm-svn: 281739
* [AArch64][GlobalISel] Add default regbank mapping for G_FCMP.Ahmed Bougacha2016-09-161-0/+10
| | | | llvm-svn: 281738
* [AArch64][GlobalISel] Add default regbank mapping for FP ops.Ahmed Bougacha2016-09-161-1/+18
| | | | | | These should have all their operands - even scalars - go on FPR. llvm-svn: 281737
* [AArch64][GlobalISel] Add default regbank mappings for mixed-type ops.Ahmed Bougacha2016-09-161-18/+36
| | | | | | | | We used to only support instructions with same-type operands. Instead, use the per-register type information to map each operand more accurately. llvm-svn: 281734
* [mips] Fix previous revert r281726.Simon Dardis2016-09-161-36/+0
| | | | llvm-svn: 281729
* Place the lowered phi instruction(s) before the DEBUG_VALUE entryKeith Walker2016-09-161-1/+1
| | | | | | | | | | | | | | | | When a phi node is finally lowered to a machine instruction it is important that the lowered "load" instruction is placed before the associated DEBUG_VALUE entry describing the value loaded. Renamed the existing SkipPHIsAndLabels to SkipPHIsLabelsAndDebug to more fully describe that it also skips debug entries. Then used the "new" function SkipPHIsAndLabels when the debug information should not be skipped when placing the lowered "load" instructions so that it is placed before the debug entries. Differential Revision: https://reviews.llvm.org/D23760 llvm-svn: 281727
* Revert "[mips] Fix aui/daui/dahi/dati for MIPSR6"Simon Dardis2016-09-167-39/+47
| | | | | | This reverts r281724. Still need dsanders to accept this. llvm-svn: 281726
* [mips] Fix aui/daui/dahi/dati for MIPSR6Simon Dardis2016-09-167-11/+75
| | | | | | | | | | | | For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 281724
* Reverting r281719, this is causing buildbot failures and timeouts again.Sjoerd Meijer2016-09-161-18/+1
| | | | llvm-svn: 281722
* [AArch64][GlobalISel] Use the generic DefaultMapping as the default.Ahmed Bougacha2016-09-161-2/+1
| | | | | | | This lets generic logic handle the common case, instead of having to implement applyMappingImpl for each instruction. llvm-svn: 281720
* This is an attempt to reapply r280808: [ARM] Lower UDIV+UREM to UDIV+MLSSjoerd Meijer2016-09-161-1/+18
| | | | | | | | | | (and the same for SREM) This was causing buildbot failures earlier (time outs in the LNT suite). However, we haven't been able to reproduce this and are suspecting this was caused by another (reverted) patch. llvm-svn: 281719
* Trying to fix Mangler memory leak in TargetLoweringObjectFile.Eric Liu2016-09-161-0/+2
| | | | | | | | | | | | | | Summary: `TargetLoweringObjectFile` can be re-used and thus `TargetLoweringObjectFile::Initialize()` can be called multiple times causing `Mang` pointer memory leak. Reviewers: echristo Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D24659 llvm-svn: 281718
* [ARM] Promote small global constants to constant poolsJames Molloy2016-09-165-3/+214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a constant is unamed_addr and is only used within one function, we can save on the code size and runtime cost of an indirection by changing the global's storage to inside the constant pool. For example, instead of: ldr r0, .CPI0 bl printf bx lr .CPI0: &format_string format_string: .asciz "hello, world!\n" We can emit: adr r0, .CPI0 bl printf bx lr .CPI0: .asciz "hello, world!\n" This can cause significant code size savings when many small strings are used in one function (4 bytes per string). This recommit contains fixes for a nasty bug related to fast-isel fallback - because fast-isel doesn't know about this optimization, if it runs and emits references to a string that we inline (because fast-isel fell back to SDAG) we will end up with an inlined string and also an out-of-line string, and we won't emit the out-of-line string, causing backend failures. It also contains fixes for emitting .text relocations which made the sanitizer bots unhappy. llvm-svn: 281715
* Move the Mangler from the AsmPrinter down to TLOF and clean up theEric Christopher2016-09-1627-136/+97
| | | | | | TLOF API accordingly. llvm-svn: 281708
* Remove unused function getMang().Eric Christopher2016-09-161-3/+0
| | | | llvm-svn: 281707
* [AArch64] Support for FP FMA when -ffp-contract=fastEvandro Menezes2016-09-151-3/+5
| | | | | | | | | | | | Currently, the machine combiner can proceed matching when -ffast-math is on. It should also match when only -ffp-contract=fast is specified as was the case before when DAGCombiner was doing the job. Patch by: Abderrazek Zaafrani <a.zaafrani@samsung.com>. Differential Revision: https://reviews.llvm.org/D24366 llvm-svn: 281649
* Revert "[ARM] Promote small global constants to constant pools"Evgeniy Stepanov2016-09-154-155/+1
| | | | | | This reverts r281604, which adds text relocations to ARM binaries. llvm-svn: 281645
* [mips][ias] Enable IAS by default for N64 on Debian mips64el.Simon Dardis2016-09-151-0/+4
| | | | | | | | | | | | | | | | | | | Unfortunately we can't enable it for all N64 because it is not yet possible to distinguish N32 from N64. N64 has been confirmed to produce identical (within reason) objects to GAS during stage 2 of compiler recursion on N64-abit Fedora. Unfortunately, Fedora's triples do not distinguish N32 from N64 so I can't enable it by default there. I'm currently repeating this testing for Debian mips64el but it's very unlikely to produce a different result. Patch by: Daniel Sanders Reviewers: sdardis Differential Review: https://reviews.llvm.org/D22678 llvm-svn: 281607
* [ARM] Promote small global constants to constant poolsJames Molloy2016-09-154-1/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a constant is unamed_addr and is only used within one function, we can save on the code size and runtime cost of an indirection by changing the global's storage to inside the constant pool. For example, instead of: ldr r0, .CPI0 bl printf bx lr .CPI0: &format_string format_string: .asciz "hello, world!\n" We can emit: adr r0, .CPI0 bl printf bx lr .CPI0: .asciz "hello, world!\n" This can cause significant code size savings when many small strings are used in one function (4 bytes per string). This recommit contains fixes for a nasty bug related to fast-isel fallback - because fast-isel doesn't know about this optimization, if it runs and emits references to a string that we inline (because fast-isel fell back to SDAG) we will end up with an inlined string and also an out-of-line string, and we won't emit the out-of-line string, causing backend failures. llvm-svn: 281604
* GlobalISel: legalize GEP instructions with small offsets.Tim Northover2016-09-151-0/+6
| | | | llvm-svn: 281602
* GlobalISel: relax type constraints on G_ICMP to allow pointers.Tim Northover2016-09-151-0/+1
| | | | llvm-svn: 281600
* GlobalISel: remove "unsized" LLTTim Northover2016-09-153-7/+5
| | | | | | | | It was only really there as a sentinel when instructions had to have precisely one type. Now that registers are typed, each register really has to have a type that is sized. llvm-svn: 281599
* GlobalISel: cache pointer sizes in LLTTim Northover2016-09-152-5/+5
| | | | | | | Otherwise everything that needs to work out what size they are has to keep a DataLayout handy, which is a bit silly and very annoying. llvm-svn: 281597
* Finish renaming remaining analyzeBranch functionsMatt Arsenault2016-09-1438-82/+80
| | | | llvm-svn: 281535
* Revert "[ARM] Promote small global constants to constant pools"Evgeniy Stepanov2016-09-144-145/+1
| | | | | | | | Breaks Android tests by introducing text relocations to ARM binaries. http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/25362/steps/run%20asan%20lit%20tests%20%5Barm%2Fbullhead-userdebug%2FMTC20F%5D/logs/stdio llvm-svn: 281526
* Revert "AMDGPU: Use SOPK compare instructions"Matt Arsenault2016-09-146-135/+51
| | | | | | Accidentally committed llvm-svn: 281514
* AMDGPU: Use SOPK compare instructionsMatt Arsenault2016-09-146-51/+135
| | | | llvm-svn: 281513
* Make analyzeBranch family of instruction names consistentMatt Arsenault2016-09-1436-60/+60
| | | | | | | analyzeBranch was renamed to use lowercase first, rename the related set to match. llvm-svn: 281506
* AArch64: Use TTI branch functions in branch relaxationMatt Arsenault2016-09-1435-240/+268
| | | | | | | | | The main change is to return the code size from InsertBranch/RemoveBranch. Patch mostly by Tim Northover llvm-svn: 281505
* [x86] fix formatting; NFCSanjay Patel2016-09-141-28/+20
| | | | llvm-svn: 281504
* [X86][SSE] Improve recognition of i64 sitofp conversions that can be ↵Simon Pilgrim2016-09-141-0/+17
| | | | | | | | | | | | performed as i32 (PR29078) Until AVX512DQ we only support i64/vXi64 sitofp conversion as scalars. This patch sees if the sign bit extends far enough that we can truncate to a i32 type and then perform sitofp without loss of precision. Differential Revision: https://reviews.llvm.org/D24345 llvm-svn: 281502
* [X86][SSE] Don't use PSHUFD directly - lower with generic shuffleSimon Pilgrim2016-09-141-17/+1
| | | | | | Remove the last user of the old getTargetShuffleNode helpers llvm-svn: 281499
* getValueType().getScalarSizeInBits() -> getScalarValueSizeInBits(), round 2 ↵Sanjay Patel2016-09-141-3/+2
| | | | | | ; NFCI llvm-svn: 281498
* getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCISanjay Patel2016-09-1412-68/+68
| | | | llvm-svn: 281495
* getValueType().getSizeInBits() -> getValueSizeInBits() ; NFCISanjay Patel2016-09-1412-58/+51
| | | | llvm-svn: 281493
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