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* [AArch64][GlobalISel] Select GPR G_SUB.Ahmed Bougacha2016-07-281-1/+6
| | | | llvm-svn: 277003
* [AArch64][GlobalISel] Select GPR G_AND.Ahmed Bougacha2016-07-281-0/+5
| | | | llvm-svn: 277002
* [GlobalISel] Remove types on selected insts instead of using LLT().Ahmed Bougacha2016-07-281-1/+1
| | | | | | | | | | LLT() has a particular meaning: it's one invalid type. But we really want selected instructions to have no type whatsoever. Also verify that types don't linger after ISel, and enable the verifier on the AArch64 select test. llvm-svn: 277001
* AMDGPU : Add intrinsics for compare with the full wavefront resultWei Ding2016-07-285-0/+103
| | | | | | Differential Revision: http://reviews.llvm.org/D22482 llvm-svn: 276998
* TargetInstrInfo: rename GetInstSizeInBytes to getInstSizeInBytes. NFCSjoerd Meijer2016-07-2823-50/+50
| | | | | | Differential Revision: https://reviews.llvm.org/D22925 llvm-svn: 276997
* [mips] Fix a warning that occurs on some gcc 4.9.2's but not all of them.Daniel Sanders2016-07-281-4/+4
| | | | llvm-svn: 276993
* Revert r276982 and r276984: [mips][fastisel] Handle 0-4 arguments without ↵Daniel Sanders2016-07-281-141/+0
| | | | | | | | | SelectionDAG It seems that the stack offset in callabi.ll varies between machines. I'll look into it. llvm-svn: 276989
* [X86] Remove CustomInserter for FMA3 instructions. Looks like since we got ↵Craig Topper2016-07-282-194/+0
| | | | | | | | full commuting support for FMAs after this was added, the coalescer can now get this right on its own. Differential Revision: https://reviews.llvm.org/D22799 llvm-svn: 276987
* [mips] Reword debug message as should have been done before committing r276982Daniel Sanders2016-07-281-1/+1
| | | | llvm-svn: 276984
* [mips][fastisel] Handle 0-4 arguments without SelectionDAG.Daniel Sanders2016-07-281-0/+141
| | | | | | | | | | | | | | | | | | | Summary: Implements fastLowerArguments() to avoid the need to fall back on SelectionDAG for 0-4 argument functions that don't do tricky things like passing double in a pair of i32's. This allows us to move all except one test to -fast-isel-abort=3. The remaining one has function prototypes of the form 'i32 (i32, double, double)' which requires floats to be passed in GPR's. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D22680 llvm-svn: 276982
* AMDGPU/SI: Don't use reserved VGPRs for SGPR spillingTom Stellard2016-07-284-6/+12
| | | | | | | | | | | | | | | Summary: We were using reserved VGPRs for SGPR spilling and this was causing some programs with a workgroup size of 1024 to use more than 64 registers, which is illegal. Reviewers: arsenm, mareko, nhaehnle Subscribers: nhaehnle, arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D22032 llvm-svn: 276980
* AMDGPU: add execfix flag to SI_ELSENicolai Haehnle2016-07-283-10/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: SI_ELSE is lowered into two parts: s_or_saveexec_b64 dst, src (at the start of the basic block) s_xor_b64 exec, exec, dst (at the end of the basic block) The idea is that dst contains the exec mask of the preceding IF block. It can happen that SIWholeQuadMode decides to switch from WQM to Exact mode inside the basic block that contains SI_ELSE, in which case it introduces an instruction s_and_b64 exec, exec, s[...] which masks out bits that can correspond to both the IF and the ELSE paths. So the resulting sequence must be: s_or_savexec_b64 dst, src s_and_b64 exec, exec, s[...] <-- added by SIWholeQuadMode s_and_b64 dst, dst, exec <-- added by SILowerControlFlow s_xor_b64 exec, exec, dst Whether to add the additional s_and_b64 dst, dst, exec is currently determined via the ExecModified tracking. With this change, it is instead determined by an additional flag on SI_ELSE which is set by SIWholeQuadMode. Finally: It also occured to me that an alternative approach for the long run is for SILowerControlFlow to unconditionally emit s_or_saveexec_b64 dst, src ... s_and_b64 dst, dst, exec s_xor_b64 exec, exec, dst and have a pass that detects and cleans up the "redundant AND with exec" pattern where possible. This could be useful anyway, because we also add instructions s_and_b64 vcc, exec, vcc before s_cbranch_scc (in moveToALU), and those are often redundant. I have some pending changes to how KILL is lowered that could also benefit from such a cleanup pass. In any case, this current patch could help in the short term with the whole ExecModified business. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D22846 llvm-svn: 276972
* Add unittests to {ARM | AArch64}TargetParser.Zijiao Ma2016-07-281-1/+1
| | | | | | | | | | | | | | Add unittest to {ARM | AArch64}TargetParser,and by the way correct problems as below: 1.Correct a incorrect indexing problem in AArch64TargetParser. The architecture enumeration is shared across ARM and AArch64 in original implementation.But In the code,I just used the index which was offset by the ARM, and this would index into the array incorrectly. To make AArch64 has its own arch enum,or we will do a lot of slowly iterating. 2.Correct a spelling error. The parameter of llvm::AArch64::getArchExtName. 3.Correct a writing mistake, in llvm::ARM::parseArchISA. Differential Revision: https://reviews.llvm.org/D21785 llvm-svn: 276957
* AMDGPU: Turn dead checks into assertsMatt Arsenault2016-07-281-9/+5
| | | | llvm-svn: 276946
* AMDGPU: Remove analyzeImmediateMatt Arsenault2016-07-283-34/+12
| | | | | | | This no longer uses the more complicated classification of constants. llvm-svn: 276945
* [Hexagon] Find speculative loop preheader in hardware loop generationKrzysztof Parzyszek2016-07-271-10/+57
| | | | | | | | Before adding a new preheader block, check if there is a candidate block where the loop setup could be placed speculatively. This will be off by default. llvm-svn: 276919
* [X86] Factor out another piece of the SAD combine. NFCI.Michael Kuperstein2016-07-271-75/+83
| | | | llvm-svn: 276918
* [Hexagon] Add option to bisect spill slot optimizationKrzysztof Parzyszek2016-07-271-2/+17
| | | | llvm-svn: 276917
* [Hexagon] Do not optimize volatile stack spill slotsKrzysztof Parzyszek2016-07-271-22/+11
| | | | llvm-svn: 276916
* [Hexagon] Handle extended versions of restore routinesKrzysztof Parzyszek2016-07-271-2/+11
| | | | llvm-svn: 276903
* XCore: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-273-14/+13
| | | | | | | Avoid implicit conversions from MachineInstrBundleIterator to MachineInstr*, mainly by preferring MachineInstr& over MachineInstr*. llvm-svn: 276899
* [MC][X86] Fix Intel Operand assembly parsing for .set idsNirav Dave2016-07-271-115/+79
| | | | | | | | | | | | | Fix intel syntax special case identifier operands that refer to a constant (e.g. .set <ID> n) to be interpreted as immediate not memory in parsing. Reviewers: rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22585 llvm-svn: 276895
* [Hexagon] Add saved callee-saved registers as live-in in non-wrapped blocksKrzysztof Parzyszek2016-07-272-8/+28
| | | | | | | | | | | | | The callee-saved registers that are saved in a function are not pristine, and so they can be defined and used. In case of shrink-wrapping though, there are blocks that are outside of the save/restore range, and in those blocks the saved registers must be treated as pristine. To avoid any uses of these registers, add them as live-in in all those blocks. This was already done for blocks reaching function exits after restore, add code that does the same for blocks reached from the function entry before save. llvm-svn: 276886
* Remove MCAsmInfo.h include from TargetOptions.hReid Kleckner2016-07-271-0/+1
| | | | | | | | | TargetOptions wants the ExceptionHandling enum. Move that to MCTargetOptions.h to avoid transitively including Dwarf.h everywhere in clang. Now you can add a DWARF tag without a full rebuild of clang semantic analysis. llvm-svn: 276883
* Typo fix. NFCDiana Picus2016-07-271-1/+1
| | | | llvm-svn: 276879
* [GlobalISel] Introduce an instruction selector.Ahmed Bougacha2016-07-277-2/+233
| | | | | | | | And implement it for AArch64, supporting x/w ADD/OR. Differential Revision: https://reviews.llvm.org/D22373 llvm-svn: 276875
* [AArch64] Mark various *Info classes as 'final'. NFC.Ahmed Bougacha2016-07-275-5/+5
| | | | llvm-svn: 276874
* [AArch64] Define AArch64RegisterInfo as a class, not a struct. NFC.Ahmed Bougacha2016-07-271-2/+1
| | | | llvm-svn: 276873
* [mips][ias] Check '$rs = $rd' constraints when both registers are in AsmText.Daniel Sanders2016-07-272-38/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is one possible solution to the problem of ignoring constraints that Simon raised in D21473 but it's a bit of a hack. The integrated assembler currently ignores violations of the tied register constraints when the operands involved in a tie are both present in the AsmText. For example, 'dati $rs, $rt, $imm' with the '$rs = $rt' will silently replace $rt with $rs. So 'dati $2, $3, 1' is processed as if the user provided 'dati $2, $2, 1' without any diagnostic being emitted. This is difficult to solve properly because there are multiple parts of the matcher that are silently forcing these constraints to be met. Tied operands are rendered to instructions by cloning previously rendered operands but this is unnecessary because the matcher was already instructed to render the operand it would have cloned. This is also unnecessary because earlier code has already replaced the MCParsedOperand with the one it was tied to (so the parsed input is matched as if it were 'dati <RegIdx 2>, <RegIdx 2>, <Imm 1>'). As a result, it looks like fixing this properly amounts to a rewrite of the tied operand handling which affects all targets. This patch however, merely inserts a checking hook just before the substitution of MCParsedOperands and the Mips target overrides it. It's not possible to accurately check the registers are the same this early (because numeric registers haven't been bound to a register class yet) so it cheats a bit and checks that the tokens that produced the operand are lexically identical. This works because tied registers need to have the same register class but it does have a flaw. It will reject 'dati $4, $a0, 1' for violating the constraint even though $a0 ends up as the same register as $4. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D21994 llvm-svn: 276867
* [PowerPC] Fix typo in PPCHazardRecognizers.cppNemanja Ivanovic2016-07-271-1/+1
| | | | | | Fixes PR28731. llvm-svn: 276865
* PowerPC: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-277-174/+170
| | | | | | | | | | | | | | | | | Avoid implicit conversions from MachineInstrBundleIterator to MachineInstr* in the PowerPC backend, mainly by preferring MachineInstr& over MachineInstr* when a pointer isn't nullable and using range-based for loops. There was one piece of questionable code in PPCInstrInfo::AnalyzeBranch, where a condition checked a pointer converted from an iterator for nullptr. Since this case is impossible (moreover, the code above guarantees that the iterator is valid), I removed the check when I changed the pointer to a reference. Despite that case, there should be no functionality change here. llvm-svn: 276864
* [ARM] Set a non-conflicting comment character for assembly in MSVC modeRenato Golin2016-07-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Currently, for ARMCOFFMCAsmInfoMicrosoft, no comment character is set, thus the idefault, '#', is used. The hash character doesn't work as comment character in ARM assembly, since '#' is used for immediate values. The comment character is set to ';', which is the comment character used by MS armasm.exe. (The microsoft armasm.exe uses a different directive syntax than what LLVM currently supports though, similar to ARM's armasm.) This allows inline assembly with immediate constants to be built (and brings the assembly output from clang -S closer to being possible to assemble). A test is added that verifies that ';' is correctly interpreted as comments in this mode, and verifies that assembling code that includes literal constants with a '#' works. Patch by Martin Storsjö. llvm-svn: 276859
* AMDGPU: Use rcp for fdiv 1, x with fpmath metadataMatt Arsenault2016-07-261-1/+1
| | | | | | | Using rcp should be OK for safe math usually, so this should not be replacing the original fdiv. llvm-svn: 276823
* AMDGPU: Use implicit_def for selecting anyextMatt Arsenault2016-07-261-4/+7
| | | | llvm-svn: 276819
* AMDGPU/R600: Remove dead custom insertersMatt Arsenault2016-07-261-209/+1
| | | | | | The intrinsics for these were removed, so this is dead. llvm-svn: 276805
* AMDGPU: Minor AsmPrinter cleanupsMatt Arsenault2016-07-261-79/+84
| | | | llvm-svn: 276804
* [Hexagon] Post-increment loads/stores enhancementsKrzysztof Parzyszek2016-07-265-112/+99
| | | | | | | - Generate vector post-increment stores more aggressively. - Predicate post-increment and vector stores in early if-conversion. llvm-svn: 276800
* [X86] Split out absdiff detection from SAD combine. NFC.Michael Kuperstein2016-07-261-59/+64
| | | | | | Preparation for supporting PSADBW emission for straight-line code. llvm-svn: 276798
* [Hexagon] Gracefully handle reg class mismatch in HexagonLoopRescheduleKrzysztof Parzyszek2016-07-261-13/+19
| | | | llvm-svn: 276793
* [Hexagon] Rerun bit tracker on new instructions in RIEKrzysztof Parzyszek2016-07-263-5/+17
| | | | | | | | | | | | | | | | | | | Consider this case: vreg1 = A2_zxth vreg0 (1) ... vreg2 = A2_zxth vreg1 (2) Redundant instruction elimination could delete the instruction (1) because the user (2) only cares about the low 16 bits. Then it could delete (2) because the input is already zero-extended. The problem is that the properties allowing each individual instruction to be deleted depend on the existence of the other instruction, so either one can be deleted, but not both. The existing check for this situation in RIE was insufficient. The fix is to update all dependent cells when an instruction is removed (replaced via COPY) in RIE. llvm-svn: 276792
* [Hexagon] Bitwise operations for insert/extract word not simplifiedKrzysztof Parzyszek2016-07-262-25/+85
| | | | | | | Change the bit simplifier to generate REG_SEQUENCE instructions in addition to COPY, which will handle cases of word insert/extract. llvm-svn: 276787
* [Hexagon] Add support for proper handling of H and L constraintsKrzysztof Parzyszek2016-07-261-8/+16
| | | | | | | | | H -> High part of reg pair. L -> Low part of reg pair. Patch by Sundeep Kushwaha. llvm-svn: 276773
* AMDGPU: Make AMDGPUMachineFunction fields privateMatt Arsenault2016-07-2610-56/+80
| | | | | | | | | ABIArgOffset is a problem because properly fsetting the KernArgSize requires that the reserved area before the real kernel arguments be correctly aligned, which requires fixing clover. llvm-svn: 276766
* AMDGPU: Add fp legacy instruction intrinsicsMatt Arsenault2016-07-265-2/+21
| | | | | | | This could use some additional optimization work to use mad/mac legacy. llvm-svn: 276764
* [mips] Fix typos in spelling of lowerRETURNADDR.Daniel Sanders2016-07-263-3/+3
| | | | | | The first letter was mistakenly capitalized. llvm-svn: 276753
* [Hexagon] Update store offset when not packetizing it with allocframeKrzysztof Parzyszek2016-07-262-15/+51
| | | | | | | | | | When the packetizer wants to put a store to a stack slot in the same packet with an allocframe, it updates the store offset to reflect the value of SP before it is updated by allocframe. If the store cannot be packetized with the allocframe after all, the offset needs to be updated back to the previous value. llvm-svn: 276749
* [ARM] Improve error messages for .arch_extension directiveOliver Stannard2016-07-261-4/+8
| | | | | | | | | | | | - More informative message when extension name is not an identifier token. - Stop parsing directive if extension is unknown (avoid duplicate error messages). - Report unsupported extensions with a source location, rather than report_fatal_error. Differential Revision: https://reviews.llvm.org/D22806 llvm-svn: 276748
* [ARM] Implement -mimplicit-it assembler optionOliver Stannard2016-07-262-38/+330
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This option, compatible with gas's -mimplicit-it, controls the generation/checking of implicit IT blocks in ARM/Thumb assembly. This option allows two behaviours that were not possible before: - When in ARM mode, emit a warning when assembling a conditional instruction that is not in an IT block. This is enabled with -mimplicit-it=never and -mimplicit-it=thumb. - When in Thumb mode, automatically generate IT instructions when an instruction with a condition code appears outside of an IT block. This is enabled with -mimplicit-it=thumb and -mimplicit-it=always. The default option is -mimplicit-it=arm, which matches the existing behaviour (allow conditional ARM instructions outside IT blocks without warning, and error if a conditional Thumb instruction is outside an IT block). The general strategy for generating IT blocks in Thumb mode is to keep a small list of instructions which should be in the IT block, and only emit them when we encounter something in the input which means we cannot continue the block. This could be caused by: - A non-predicable instruction - An instruction with a condition not compatible with the IT block - The IT block already contains 4 instructions - A branch-like instruction (including ALU instructions with the PC as the destination), which cannot appear in the middle of an IT block - A label (branching into an IT block is not legal) - A change of section, architecture, ISA, etc - The end of the assembly file. Some of these, such as change of section and end of file, are parsed outside of the ARM asm parser, so I've added a new virtual function to AsmParser to ensure any previously-parsed instructions have been emitted. The ARM implementation of this flushes the currently pending IT block. We now have to try instruction matching up to 3 times, because we cannot know if the current IT block is valid before matching, and instruction matching changes depending on the IT block state (due to the 16-bit ALU instructions, which set the flags iff not in an IT block). In the common case of not having an open implicit IT block and the instruction being matched not needing one, we still only have to run the matcher once. I've removed the ITState.FirstCond variable, because it does not store any information that isn't already represented by CurPosition. I've also updated the comment on CurPosition to accurately describe it's meaning (which this patch doesn't change). Differential Revision: https://reviews.llvm.org/D22760 llvm-svn: 276747
* [X86][SSE] Fixed issue with memory folding of (v)cvtsd2ss intrinsicsSimon Pilgrim2016-07-261-2/+2
| | | | | | | | Fixed typo in the intrinsic definitions of (v)cvtsd2ss with memory folding. This was only unearthed when rL276102 started using the intrinsic again..... llvm-svn: 276740
* [mips] MIPS64R6 compact branch supportSimon Dardis2016-07-265-11/+98
| | | | | | | | | | | | | MIPS64R6 compact branch support. As the MIPS LLVM backend uses distinct MachineInstrs for certain 32 and 64 bit instructions (e.g. BEQ & BEQ64) that map to the same instruction, extend compact branch support for the corresponding 64bit branches. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D20164 llvm-svn: 276739
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