summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* Expand misc operations from test/CodeGen/Generic.Eli Friedman2009-07-171-0/+17
| | | | llvm-svn: 76163
* Handle void in XCoreTargetLowering::isLegalAddressingMode. Triggers in Eli Friedman2009-07-171-0/+5
| | | | | | test/CodeGen/Generic. llvm-svn: 76162
* Remove some unnecessary expansion markings. Add a few expansion Eli Friedman2009-07-171-24/+7
| | | | | | markings that show up in test/CodeGen/Generic. llvm-svn: 76160
* Add operation expansion/promotion for a bunch of operations, many of Eli Friedman2009-07-171-5/+54
| | | | | | which show up in test/CodeGen/Generic. llvm-svn: 76158
* Fix tSUBspi operand definition. It reads and writes sp, which is a high ↵Evan Cheng2009-07-171-1/+1
| | | | | | register. llvm-svn: 76155
* Set an operation expansion, noticed while running Eli Friedman2009-07-171-0/+2
| | | | | | llc over test/CodeGen/Generic with -march=alpha. llvm-svn: 76154
* One more operation expansion for MIPS, from test/CodeGen/Generic.Eli Friedman2009-07-171-1/+2
| | | | llvm-svn: 76149
* Make sure CWriter's Context get's initialized.Daniel Dunbar2009-07-171-0/+2
| | | | llvm-svn: 76147
* Expand a bunch of illegal operations on MIPS (found by Eli Friedman2009-07-171-0/+12
| | | | | | inspection and running over CodeGen/Generic). llvm-svn: 76146
* Fix 'may be used uninitialized' warning.Daniel Dunbar2009-07-171-2/+2
| | | | | | - Anton, please review. llvm-svn: 76144
* Emit cross regclass register moves for thumb2.Anton Korobeynikov2009-07-166-27/+40
| | | | | | Minor code duplication cleanup. llvm-svn: 76124
* GV with ghost linkage (module being lazily streamed in in JIT lazy ↵Evan Cheng2009-07-161-5/+9
| | | | | | compilation mode) do not require extra load from stub. This fixes ExecutionEngine/2005-12-02-TailCallBug.ll. llvm-svn: 76121
* Silence warning in Linux builds:Jakob Stoklund Olesen2009-07-161-2/+3
| | | | | | X86InstrInfo.cpp:2272: warning: suggest explicit braces to avoid ambiguous 'else' llvm-svn: 76105
* Add line numbers to OProfile. To do this, I added a processDebugLoc()Jeffrey Yasskin2009-07-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | call to the MachineCodeEmitter interface and made copying the start line of a function not conditional on whether we're emitting Dwarf debug information. I'll propagate the processDebugLoc() calls to the non-X86 targets in a followup patch. In the long run, it'll probably be better to gather this information through the DwarfWriter, but the DwarfWriter currently depends on the AsmPrinter and TargetAsmInfo, and fixing that would be out of the way for this patch. There's a bug in OProfile 0.9.4 that makes it ignore line numbers for addresses above 4G, and a patch fixing it at http://thread.gmane.org/gmane.linux.oprofile/7634 Sample output: $ sudo opcontrol --reset; sudo opcontrol --start-daemon; sudo opcontrol --start; `pwd`/Debug/bin/lli fib.bc; sudo opcontrol --stop Signalling daemon... done Profiler running. fib(40) == 165580141 Stopping profiling. $ opreport -g -d -l `pwd`/Debug/bin/lli|head -60 Overflow stats not available CPU: Core 2, speed 1998 MHz (estimated) Counted CPU_CLK_UNHALTED events (Clock cycles when not halted) with a unit mask of 0x00 (Unhalted core cycles) count 100000 vma samples % linenr info image name symbol name 00007f67a30370b0 25489 61.2554 fib.c:24 10946.jo fib_left 00007f67a30370b0 1634 6.4106 fib.c:24 00007f67a30370b1 83 0.3256 fib.c:24 00007f67a30370b9 1997 7.8348 fib.c:24 00007f67a30370c6 2080 8.1604 fib.c:27 00007f67a30370c8 988 3.8762 fib.c:27 00007f67a30370cd 1315 5.1591 fib.c:27 00007f67a30370cf 251 0.9847 fib.c:27 00007f67a30370d3 1191 4.6726 fib.c:27 00007f67a30370d6 975 3.8252 fib.c:27 00007f67a30370db 1010 3.9625 fib.c:27 00007f67a30370dd 242 0.9494 fib.c:27 00007f67a30370e1 2782 10.9145 fib.c:28 00007f67a30370e5 3768 14.7828 fib.c:28 00007f67a30370eb 615 2.4128 (no location information) 00007f67a30370f3 6558 25.7287 (no location information) 00007f67a3037100 15603 37.4973 fib.c:29 10946.jo fib_right 00007f67a3037100 1646 10.5493 fib.c:29 00007f67a3037101 45 0.2884 fib.c:29 00007f67a3037109 2372 15.2022 fib.c:29 00007f67a3037116 2234 14.3178 fib.c:32 00007f67a3037118 612 3.9223 fib.c:32 00007f67a303711d 622 3.9864 fib.c:32 00007f67a303711f 385 2.4675 fib.c:32 00007f67a3037123 404 2.5892 fib.c:32 00007f67a3037126 634 4.0633 fib.c:32 00007f67a303712b 870 5.5759 fib.c:32 00007f67a303712d 62 0.3974 fib.c:32 00007f67a3037131 1848 11.8439 fib.c:33 00007f67a3037135 2840 18.2016 fib.c:33 00007f67a303713a 1 0.0064 fib.c:33 00007f67a303713b 1023 6.5564 (no location information) 00007f67a3037143 5 0.0320 (no location information) 000000000080c1e4 15 0.0360 MachineOperand.h:150 lli llvm::MachineOperand::isReg() const 000000000080c1e4 6 40.0000 MachineOperand.h:150 000000000080c1ec 2 13.3333 MachineOperand.h:150 ... llvm-svn: 76102
* With recent MC changes, RIP base register is explicitly modeled. Make sure ↵Evan Cheng2009-07-161-7/+9
| | | | | | we add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load) into the use instruction. llvm-svn: 76094
* UnbreakAnton Korobeynikov2009-07-1611-56/+122
| | | | llvm-svn: 76064
* Temporary disable 16 bit bswapAnton Korobeynikov2009-07-161-3/+4
| | | | llvm-svn: 76063
* Add instruction formats and few opcodesAnton Korobeynikov2009-07-162-983/+705
| | | | llvm-svn: 76062
* Add bswap patternsAnton Korobeynikov2009-07-161-0/+18
| | | | llvm-svn: 76061
* Provide crazy pseudos for regpairs spills / reloadsAnton Korobeynikov2009-07-162-2/+47
| | | | llvm-svn: 76060
* Handle long-disp stuff more consistentlyAnton Korobeynikov2009-07-163-7/+31
| | | | llvm-svn: 76059
* All FP instructions have 12 bit memory displacement fieldAnton Korobeynikov2009-07-161-34/+34
| | | | llvm-svn: 76058
* Another predicate routineAnton Korobeynikov2009-07-162-0/+31
| | | | llvm-svn: 76057
* More helpersAnton Korobeynikov2009-07-162-0/+66
| | | | llvm-svn: 76056
* Add bunch of branch folding stuffAnton Korobeynikov2009-07-163-1/+187
| | | | llvm-svn: 76055
* Add missed opcodes to short => long displacement conversionAnton Korobeynikov2009-07-161-0/+2
| | | | llvm-svn: 76054
* CleanupAnton Korobeynikov2009-07-161-91/+29
| | | | llvm-svn: 76053
* Fix logic inversion for RI-mode address selectionAnton Korobeynikov2009-07-161-1/+1
| | | | llvm-svn: 76052
* Expand 32-bit bitconverts via memoryAnton Korobeynikov2009-07-161-2/+2
| | | | llvm-svn: 76050
* Fix incomin arg stack frame offset in case we need to generate stack frameAnton Korobeynikov2009-07-161-1/+1
| | | | llvm-svn: 76049
* Fix instruction mnemonics for some fp_to_sint operationsAnton Korobeynikov2009-07-161-2/+2
| | | | llvm-svn: 76048
* i32 values are passed extended also on stack. Handle this in generic wayAnton Korobeynikov2009-07-161-23/+24
| | | | llvm-svn: 76047
* We definitely have 1-0 boolsAnton Korobeynikov2009-07-161-0/+1
| | | | llvm-svn: 76046
* Revert the commit, it just hides the real bugAnton Korobeynikov2009-07-161-1/+2
| | | | llvm-svn: 76045
* Out GR128 regclass is not a 'real' i128 one.Anton Korobeynikov2009-07-163-5/+4
| | | | llvm-svn: 76044
* Add missed condbranch opcodesAnton Korobeynikov2009-07-161-5/+29
| | | | llvm-svn: 76043
* Handle bitconvertsAnton Korobeynikov2009-07-163-4/+16
| | | | llvm-svn: 76042
* Unbreak mvi and friends - emit only 'significant' part of the operandAnton Korobeynikov2009-07-162-6/+17
| | | | llvm-svn: 76041
* Expand fp_to_uint tooAnton Korobeynikov2009-07-161-0/+3
| | | | llvm-svn: 76040
* We don't have FP truncstoresAnton Korobeynikov2009-07-161-0/+3
| | | | llvm-svn: 76039
* Expand uint_to_fpAnton Korobeynikov2009-07-161-0/+2
| | | | llvm-svn: 76038
* Emit proper rounding mode for fp_to_sintAnton Korobeynikov2009-07-161-4/+4
| | | | llvm-svn: 76037
* f32/f64 regs are stored on stack if we're short in FP regsAnton Korobeynikov2009-07-161-2/+2
| | | | llvm-svn: 76036
* Lower anyext to zext, 32-bit stuff does not have any implicit zero-extension ↵Anton Korobeynikov2009-07-161-2/+1
| | | | | | side effects llvm-svn: 76035
* Make FP zero to be legal FP immediate via LOAD ZEROAnton Korobeynikov2009-07-162-0/+48
| | | | llvm-svn: 76034
* Loads are not two-address in any wayAnton Korobeynikov2009-07-161-8/+7
| | | | llvm-svn: 76033
* Add LOAD NEGATIVE instructionAnton Korobeynikov2009-07-161-1/+9
| | | | llvm-svn: 76032
* LOAD COMPLEMENT instruction is not really two-addrAnton Korobeynikov2009-07-161-4/+5
| | | | llvm-svn: 76031
* Add multiple add/sub instructionsAnton Korobeynikov2009-07-161-0/+40
| | | | llvm-svn: 76030
* Handle FP callee-saved regsAnton Korobeynikov2009-07-163-51/+102
| | | | llvm-svn: 76029
OpenPOWER on IntegriCloud