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* [CodeGen] Mark setjmp/catchret MBBs address-takenJoseph Tremoulet2015-10-232-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This ensures that BranchFolding (and similar) won't remove these blocks. Also allow AsmPrinter::EmitBasicBlockStart to process MBBs which are address-taken but do not have BBs that are address-taken, since otherwise its call to getAddrLabelSymbolTableToEmit would fail an assertion on such blocks. I audited the other callers of getAddrLabelSymbolTableToEmit (and getAddrLabelSymbol); they all have BBs known to be address-taken except for the call through getAddrLabelSymbol from WinException::create32bitRef; that call is actually now unreachable, so I've removed it and updated the signature of create32bitRef. This fixes PR25168. Reviewers: majnemer, andrew.w.kaylor, rnk Subscribers: pgavlin, llvm-commits Differential Revision: http://reviews.llvm.org/D13774 llvm-svn: 251113
* Revert "[AArch64]Merge halfword loads into a 32-bit load"James Molloy2015-10-231-215/+45
| | | | | | This reverts commit r250719. This introduced a codegen fault in SPEC2000.gcc, when compiled for Cortex-A53. llvm-svn: 251108
* [mips][microMIPS] Implement SHLL.PH, SHLL_S.PH, SHLL.QB, SHLLV.PH, ↵Zlatko Buljan2015-10-233-32/+126
| | | | | | | | SHLLV_S.PH, SHLLV.QB, SHLLV_S.W, SHLL_S.W, SHRA.QB and SHRA_R.QB instructions Differential Revision: http://reviews.llvm.org/D13929 llvm-svn: 251098
* AArch64: Disable the latency heuristicMatthias Braun2015-10-221-0/+5
| | | | | | | | | | | | It turned out not to improve any of our benchmarks but occasionally led to increased register pressure and spilling. Only enabling for the Cyclone CPU as the results on the cortex CPUs give mixed results. Differential Revision: http://reviews.llvm.org/D13708 llvm-svn: 251038
* Remove the last traces of X86CompilationCallback as it is completelyEric Christopher2015-10-222-78/+0
| | | | | | unused. llvm-svn: 251035
* Change makeLibCall to take an ArrayRef<SDValue> instead of pointer and size. ↵Craig Topper2015-10-223-13/+11
| | | | | | This removes the need to pass a hardcoded size in many places. NFC llvm-svn: 251032
* [PPC] Fix PR24686 by failing assembly for an invalid relocationBill Schmidt2015-10-221-0/+7
| | | | | | | | | | | | PR24686 identifies a problem where a relocation expression is invalid when not all of the symbols in the expression can be locally resolved. This causes the compiler to request a PC-relative half16ds relocation, which is nonsensical for PowerPC. This patch recognizes this situation and ensures we fail the assembly cleanly. Test case provided by Anton Blanchard. llvm-svn: 251027
* [X86][AVX512] extend vcvtph2ps to support xmm/ymm and sae versionsAsaf Badouh2015-10-223-14/+45
| | | | | | Differential Revision: http://reviews.llvm.org/D13945 llvm-svn: 251018
* AVX-512: Fixed a bug in select_cc for i1 typeElena Demikhovsky2015-10-221-0/+1
| | | | | | | | | | | Fixed faiure: LLVM ERROR: Cannot select: t33: i1 = select_cc t25, Constant:i32<0>, t45, t42, seteq:ch added a test Differential Revision: http://reviews.llvm.org/D13943 llvm-svn: 250996
* Partially reverted changes from r250686Elena Demikhovsky2015-10-221-2/+4
| | | | | | | | Clang runtime failure was reported. Assertion failed: (isExtended() && "Type is not extended!"), function getTypeForEVT I'll need to add a proper handling for PointerType in masked load/store intrinsics. llvm-svn: 250995
* WebAssembly: fix more syntaxJF Bastien2015-10-222-5/+5
| | | | | | | br_if shouldn't start with a dot. div and rem went from prefix u/s to suffix. llvm-svn: 250972
* Add missing load/store flags to thumb2 instructions.Pete Cooper2015-10-221-1/+4
| | | | | | | | | | | | | | | | | | These were the cause of a verifier error when building 7zip with -verify-machineinstrs. Running 'make check' with the verifier triggered the same error on the test here so i've updated the test to run the verifier on one of its runs instead of adding a new one. While looking at this code, there was a stale comment that these instructions were only used for disassembly. This probably used to be the case, but they are now used in the 'ARM load / store optimization pass' too. This reapplies r242300 which was reverted in r242428 due to bot failures. Ultimately those failures were spurious and completely unrelated to this commit. I reverted this at the time because it was thought to be at fault. llvm-svn: 250969
* AMDGPU: Fix adding redundant m0 usesMatt Arsenault2015-10-211-2/+0
| | | | | | BuildMI already adds these since they are defined correctly now. llvm-svn: 250961
* AMDGPU: Fix verifier error in SIFoldOperandsMatt Arsenault2015-10-211-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | There may be other use operands that also need their kill flags cleared. This happens in a few tests when SIFoldOperands is moved after PeepholeOptimizer. PeepholeOptimizer rewrites cases that look like: %vreg0 = ... %vreg1 = COPY %vreg0 use %vreg1<kill> %vreg2 = COPY %vreg0 use %vreg2<kill> to use the earlier source to %vreg0 = ... use %vreg0 use %vreg0 Currently SIFoldOperands sees the copied registers, so there is only one use. So far I haven't managed to come up with a test that currently has multiple uses of a foldable VGPR -> VGPR copy. llvm-svn: 250960
* AMDGPU: Split DiagnosticInfoUnsupported into its own fileMatt Arsenault2015-10-214-41/+76
| | | | llvm-svn: 250959
* AMDGPU: Simplify VOP3 operand legalization.Matt Arsenault2015-10-213-42/+58
| | | | | | | | | | | | | | | | | | | | | | | | | This was checking for a variety of situations that should never happen. This saves a tiny bit of compile time. We should not be selecting instructions with invalid operands in the first place. Most of the time for registers copys are inserted to the correct operand register class. For VOP3, since all operand types are supported and literal constants never are, we just need to verify the constant bus requirements (all immediates should be legal inline ones). The only possibly tricky case to maybe worry about is if when legalizing operands in moveToVALU with s_add_i32 and similar instructions. If the original s_add_i32 had a literal constant and we need to replace it with v_add_i32_e64 we would have an unsupported literal operand. However, I don't think we should worry about that because SIFoldOperands should handle folding literal constant operands into the SALU instructions based on the uses. At SIFoldOperands time, the legality and profitability of operand types is a bit different. llvm-svn: 250951
* AMDGPU: Fix not checking implicit operands in verifyInstructionMatt Arsenault2015-10-211-15/+29
| | | | | | | When verifying constant bus restrictions, this wasn't catching uses in implicit operands. llvm-svn: 250948
* Drop assert that a call with struct return goes to a function with sretJoerg Sonnenberger2015-10-211-2/+2
| | | | | | | attribute. Clang incorrectly misses it on __muldc3 and friends and the type system doesn't include it properly either. llvm-svn: 250938
* [x86] move recursive add match for LEA to helper function; NFCISanjay Patel2015-10-211-30/+37
| | | | llvm-svn: 250926
* [X86] Add AMD mwaitx, monitorx, and clzero instructions to the assembly ↵Craig Topper2015-10-211-0/+26
| | | | | | parser and disassembler. llvm-svn: 250911
* [mips][mips16] Re-work the inline assembly stubs to work with IAS. NFC.Daniel Sanders2015-10-211-89/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Previously, we were inserting an InlineAsm statement for each line of the inline assembly. This works for GAS but it triggers prologue/epilogue emission when IAS is in use. This caused: .set noreorder .cpload $25 to be emitted as: .set push .set reorder .set noreorder .set pop .set push .set reorder .cpload $25 .set pop which led to assembler errors and caused the test to fail. The whitespace-after-comma changes included in this patch are necessary to match the output when IAS is in use. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13653 llvm-svn: 250895
* [mips][msa] Remove copy_u.d and move copy_u.w to MSA64.Daniel Sanders2015-10-213-5/+32
| | | | | | | | | | | | | | | | | | | | | | | Summary: The forwards compatibility strategy employed by MIPS is to consider registers to be infinitely sign-extended. Then on ISA's with a wider register, the result of existing instructions are sign-extended to register width and zero-extended counterparts are added. copy_u.w on MSA32 and copy_u.w on MSA64 violate this strategy and we have therefore corrected the MSA specs to fix this. We still keep track of sign/zero-extension during legalization but we now match copy_s.[wd] where required. No change required to clang since __builtin_msa_copy_u_[wd] will map to copy_s.[wd] where appropriate for the target. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13472 llvm-svn: 250887
* Do not use `dyn_cast<X>` after `isa<X>` (NFC)Mehdi Amini2015-10-211-1/+1
| | | | | From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 250883
* WebAssembly: support importsJF Bastien2015-10-211-1/+23
| | | | | | C/C++ code can declare an extern function, which will show up as an import in WebAssembly's output. It's expected that the linker will resolve these, and mark unresolved imports as call_import (I have a patch which does this in wasmate). llvm-svn: 250875
* [Hexagon] Bit-based instruction simplificationKrzysztof Parzyszek2015-10-203-0/+2793
| | | | | | | Analyze bit patterns of operands and values of instructions to perform various simplifications, dead/redundant code elimination, etc. llvm-svn: 250868
* [Hexagon] Fix isNVStorable flag in .td filesKrzysztof Parzyszek2015-10-202-20/+48
| | | | | | | An upper half and a double word cannot be used as value sources in a new-value store. llvm-svn: 250867
* [Hexagon] Capture aggregate variables by reference, not valueKrzysztof Parzyszek2015-10-201-1/+1
| | | | llvm-svn: 250851
* [Hexagon] Do not fall-through if there is no CFG edgeKrzysztof Parzyszek2015-10-201-1/+1
| | | | llvm-svn: 250850
* [Hexagon] Use symbolic name for subregister instead of hardcoded numberKrzysztof Parzyszek2015-10-201-1/+1
| | | | llvm-svn: 250849
* [Hexagon] Change Based->Base in getBasedWithImmOffsetKrzysztof Parzyszek2015-10-202-3/+3
| | | | llvm-svn: 250848
* [Hexagon] Remove the remnants of isConstExtProfitableKrzysztof Parzyszek2015-10-207-125/+27
| | | | llvm-svn: 250845
* [SystemZ] Use LivePhysRegs helper class in SystemZShortenInst.cpp.Jonas Paulsson2015-10-201-80/+35
| | | | | | | | | Don't use home brewed liveness tracking code for phys regs, since this class does the job. Reviewed by Ulrich Weigand. llvm-svn: 250829
* Adding support for TargetLoweringBase::LibCallArtyom Skrobov2015-10-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: TargetLoweringBase::Expand is defined as "Try to expand this to other ops, otherwise use a libcall." For ISD::UDIV and ISD::SDIV, the choice between the two possibilities was defined in a rather convoluted way: - if DIVREM is legal, expand to DIVREM - if DIVREM has a custom lowering, expand to DIVREM - if DIVREM libcall is defined and a remainder from the same division is computed elsewhere, expand to a DIVREM libcall - else, expand to a DIV libcall This had the undesirable effect that if both DIV and DIVREM are implemented as libcalls, then ISD::UDIV and ISD::SDIV are expanded to the heavier DIVREM libcall, even when the remainder isn't used. The new code adds a new LegalizeAction, TargetLoweringBase::LibCall, so that backends can directly control whether they prefer an expansion or a conversion to a libcall. This makes the generic lowering code even more generic, allowing its reuse in a wider range of target-specific configurations. The useful effect is that ARM backend will now generate a call to __aeabi_{i,u}div rather than __aeabi_{i,u}divmod in cases where it doesn't need the remainder. There's no functional change outside the ARM backend. Reviewers: t.p.northover, rengolin Subscribers: t.p.northover, llvm-commits, aemerson Differential Revision: http://reviews.llvm.org/D13862 llvm-svn: 250826
* AVX512: Implemented encoding and intrinsics for VPBROADCASTB/W/D/Q instructions.Igor Breger2015-10-203-106/+109
| | | | | | Differential Revision: http://reviews.llvm.org/D13884 llvm-svn: 250819
* AMDGPU: Add MachineInstr overloads for instruction format testsMatt Arsenault2015-10-207-40/+111
| | | | llvm-svn: 250797
* AMDGPU: Stop reserving v[254:255]Matt Arsenault2015-10-201-4/+0
| | | | | | | | | | | This wasn't doing anything useful. They weren't explicitly used anywhere, and the RegScavenger ignores reserved registers. This for some reason caused a random scheduling change in the test. Getting the check lines to pass is too frustrating, and there's probably not too much value in checking the vector case's operands N times. llvm-svn: 250794
* WebAssembly: fix call/return syntax.JF Bastien2015-10-201-1/+6
| | | | | | They are now typeless, unlike other operations. llvm-svn: 250793
* MSP430: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-202-5/+3
| | | | llvm-svn: 250792
* SystemZ: Remove implicit ilist iterator conversion, NFCDuncan P. N. Exon Smith2015-10-201-1/+1
| | | | llvm-svn: 250790
* XCore: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-202-8/+4
| | | | llvm-svn: 250788
* PowerPC: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-205-27/+23
| | | | llvm-svn: 250787
* Sparc: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-202-5/+4
| | | | llvm-svn: 250781
* NVPTX: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-207-25/+20
| | | | llvm-svn: 250779
* Hexagon: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-2016-38/+34
| | | | | | | | | | | | | | | | | | | There are two things out of the ordinary in this commit. First, I made a loop obviously "infinite" in HexagonInstrInfo.cpp. After checking if an instruction was at the beginning of a basic block (in which case, `break`), the loop decremented and checked the iterator for `nullptr` as the loop condition. This has never been possible (the prev pointers are always been circular, so even with the weird ilist/iplist implementation, this isn't been possible), so I removed the condition. Second, in HexagonAsmPrinter.cpp there was another case of comparing a `MachineBasicBlock::instr_iterator` against `MachineBasicBlock::end()` (which returns `MachineBasicBlock::iterator`). While not incorrect, it's fragile. I switched this to `::instr_end()`. All that said, no functionality change intended here. llvm-svn: 250778
* WebAssembly: fix syntax for br_if.JF Bastien2015-10-203-5/+5
| | | | llvm-svn: 250777
* Mips: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-209-40/+29
| | | | llvm-svn: 250769
* CppBackend: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-201-37/+26
| | | | | | | Mostly just converted to range-based for loops. May have converted a couple of extra loops as a drive-by (not sure). llvm-svn: 250766
* BPF: Remove implicit ilist iterator conversion, NFCDuncan P. N. Exon Smith2015-10-201-2/+1
| | | | llvm-svn: 250765
* ARM: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-199-45/+40
| | | | llvm-svn: 250759
* X86: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-198-31/+24
| | | | llvm-svn: 250741
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