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* CodeGen: rename Win64 ExceptionHandling to WinEHSaleem Abdulrasool2014-06-292-10/+10
| | | | | | | | | | This exception format is not specific to Windows x64. A similar approach is taken on nearly all architectures. Generalise the name to reflect reality. This will eventually be used for Windows on ARM data emission as well. Switch the enum and namespace into an enum class. llvm-svn: 212000
* MC: rename EmitWin64EH routinesSaleem Abdulrasool2014-06-292-15/+13
| | | | | | | | | | | | | | | Rename the routines to reflect the reality that they are more related to call frame information than to Win64 EH. Although EH is implemented in an intertwined manner by augmenting with an exception handler and an associated parameter, the majority of these routines emit information required to unwind the frames. This also helps identify that these routines are generic for most windows platforms (they apply equally to nearly all architectures except x86) although the encoding of the information is architecture dependent. Unwinding data is emitted via EmitWinCFI* and exception handling information via EmitWinEH*. llvm-svn: 211994
* Add ops() method to SDNode that returns an ArrayRef<SDUse>. Use it to ↵Craig Topper2014-06-292-11/+8
| | | | | | simplify some code. llvm-svn: 211993
* [x86] Fix a bug in the v8i16 shuffling exposed by the new splat-likeChandler Carruth2014-06-281-1/+1
| | | | | | | | | | | lowering for v16i8. ASan and some bots caught this bug with existing test cases. Fixing it even fixed a miscompile with one of the test cases. I'm still a bit suspicious of this test case as I've not taken a proper amount of time to think about it, but the fix here is strict goodness. llvm-svn: 211976
* [x86] Add handling for splat-like widenings of v16i8 shuffles.Chandler Carruth2014-06-281-0/+80
| | | | | | | | | | | | | | | | These show up really frequently, not the least with actual splats. =] We lowered these quite badly before. The new code path tries to widen i8 shuffles to i16 shuffles in a splat-like way. There are still some inefficiencies in our i16 splat logic though, so we aren't really done here. Also, for certain patterns (bit of a gather-and-splat) we still generate pretty silly code, and I've left a fixme for addressing it. However, I'm not actually worried about this code pattern as much. The old shuffle lowering generates a 29 instruction monstrosity for it that should execute much more slowly. llvm-svn: 211974
* [x86] Fix another bug hit when bootstrapping with the new shuffleChandler Carruth2014-06-271-1/+1
| | | | | | | | | | | | | lowering. For maximum irony, I had already discovered this bug, diagnosed it, and left FIXMEs about it in the test cases. =[ I just failed to go back over those until after i had reduced a bootstrap miscompile down to a single TU, stared at the assembly for an hour, and figured out the bug. Again. Oh well. llvm-svn: 211955
* [NVPTX] Use GreatestCommonDivisor64 from MathExtras instead of using our ↵Justin Holewinski2014-06-271-14/+4
| | | | | | own. Thanks Hal! llvm-svn: 211952
* [NVPTX] Add reflect intrinsic (better than matching by function name)Justin Holewinski2014-06-271-22/+47
| | | | | | Also clean up some of the logic in NVVMReflect.cpp while we're messing around in there. llvm-svn: 211948
* [NVPTX] Handle all possible vector types in getSetCCResultType, not just the ↵Justin Holewinski2014-06-271-2/+2
| | | | | | ones representable as MVTs llvm-svn: 211947
* [NVPTX] Add 'b' asm constraintJustin Holewinski2014-06-271-0/+3
| | | | llvm-svn: 211946
* [NVPTX] Simplify some argument lowering logicJustin Holewinski2014-06-271-13/+8
| | | | llvm-svn: 211945
* [NVPTX] Do not process samplers in GenericToNVVMJustin Holewinski2014-06-271-1/+1
| | | | llvm-svn: 211944
* [NVPTX] Error out if initializer is given for variable in an address space ↵Justin Holewinski2014-06-271-7/+18
| | | | | | that does not support initialization llvm-svn: 211943
* [NVPTX] Add support for .managed variables for UVMJustin Holewinski2014-06-271-0/+5
| | | | llvm-svn: 211942
* [NVPTX] Emit .weak linkage for link_once, weak, available_externally, and ↵Justin Holewinski2014-06-271-0/+4
| | | | | | common linkage llvm-svn: 211941
* [NVPTX] Variables that start with llvm. or nvvm. are reserved and should not ↵Justin Holewinski2014-06-271-0/+5
| | | | | | be emitted llvm-svn: 211940
* [NVPTX] Fix handling of ldg/ldu intrinsics.Justin Holewinski2014-06-274-100/+375
| | | | | | | | | | The address space of the pointer must be global (1) for these intrinsics. There must also be alignment metadata attached to the intrinsic calls, e.g. %val = tail call i32 @llvm.nvvm.ldu.i.global.i32.p1i32(i32 addrspace(1)* %ptr), !align !0 !0 = metadata !{i32 4} llvm-svn: 211939
* [NVPTX] Clean up argument lowering code and properly handle alignment for ↵Justin Holewinski2014-06-271-90/+76
| | | | | | structs and vectors llvm-svn: 211938
* [NVPTX] Add missing boolean vector contents flagJustin Holewinski2014-06-271-0/+1
| | | | llvm-svn: 211937
* [NVPTX] Add support for [SHL,SRA,SRL]_PARTSJustin Holewinski2014-06-273-0/+170
| | | | llvm-svn: 211936
* [NVPTX] Implement fma and imad contraction as target DAGCombiner patternsJustin Holewinski2014-06-274-126/+549
| | | | | | This also introduces DAGCombiner patterns for mul.wide to multiply two smaller integers and produce a larger integer llvm-svn: 211935
* [NVPTX] Add support for efficient rotate instructions on SM 3.2+Justin Holewinski2014-06-272-4/+170
| | | | llvm-svn: 211934
* [NVPTX] Add missing isel patterns for 64-bit atomicsJustin Holewinski2014-06-271-0/+98
| | | | llvm-svn: 211933
* [NVPTX] Add isel patterns for bit-field extract (bfe)Justin Holewinski2014-06-273-0/+238
| | | | llvm-svn: 211932
* [NVPTX] Add support for isspacep instructionJustin Holewinski2014-06-272-0/+40
| | | | llvm-svn: 211931
* [NVPTX] Add support for envreg readsJustin Holewinski2014-06-272-1/+45
| | | | llvm-svn: 211930
* [NVPTX] Add target options for PTX 3.2/4.0 and SM 5.0 (Maxwell)Justin Holewinski2014-06-272-7/+11
| | | | | | Default PTX version is set to PTX 3.2 llvm-svn: 211929
* [NVPTX] Update sub-target feature detectionJustin Holewinski2014-06-271-3/+5
| | | | llvm-svn: 211928
* [NVPTX] Directly control the Machine SSA passes that are invoked for NVPTX.Justin Holewinski2014-06-271-0/+41
| | | | | | | NVPTX is a bit special in the optimizations it requires, so this gives us better control over the backend optimization pipeline. llvm-svn: 211927
* [NVPTX] Emit .weak when linkage is not external, internal, or privateJustin Holewinski2014-06-271-0/+7
| | | | llvm-svn: 211926
* [NVPTX] Just use getTypeAllocSize() when computing return value size for ↵Justin Holewinski2014-06-271-17/+1
| | | | | | structures and vectors llvm-svn: 211925
* [x86] Fix a miscompile in the new shuffle lowering uncovered byChandler Carruth2014-06-271-13/+13
| | | | | | | | | a bootstrap. I managed to mis-remember how PACKUS worked on x86, and was using undef for the high bytes instead of zero. The fix is fairly obvious. llvm-svn: 211922
* R600: Move trivial getters into header, use initializer listMatt Arsenault2014-06-272-95/+82
| | | | llvm-svn: 211917
* [FastISel][X86] Fix typos.Juergen Ributzka2014-06-271-13/+13
| | | | llvm-svn: 211911
* R600: Don't crash on unhandled instruction in promote allocaMatt Arsenault2014-06-271-2/+24
| | | | llvm-svn: 211906
* Clean up unused variable warning in release build.Alexander Kornienko2014-06-271-0/+1
| | | | llvm-svn: 211902
* [PowerPC] Constrain base register in PPCRegisterInfo::resolveFrameIndexUlrich Weigand2014-06-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | I've run into a bug where current LLVM at -O0 (with fast-isel) generated invalid code like: ld 0, 20936(1) # 8-byte Folded Reload stw 12, 10348(0) stw 12, 10344(0) The underlying vreg had been introduced as base register by the Local Stack Slot Allocation pass. That register was constrained to G8RC by PPCRegisterInfo::materializeFrameBaseRegister to match the ADDI instruction used to set it, but it was *not* constrained to G8RC_NOX0 to fit the *use* of the register in an address. That should have happened in PPCRegisterInfo::resolveFrameIndex. This patch adds an appropriate constrainRegClass call. Reviewed by Hal Finkel. llvm-svn: 211897
* [x86] Clean up some unused variables, especially in release builds.Chandler Carruth2014-06-271-9/+6
| | | | llvm-svn: 211894
* [x86] Teach the target combine step to aggressively fold pshufd insturcions.Chandler Carruth2014-06-271-11/+77
| | | | | | | | | | | | | Summary: This allows it to fold pshufd instructions across intervening half-shuffles and other noise. This pattern actually shows up in the generic lowering tests, but I've also added direct tests using intrinsics to make sure that the specific desired functionality is working even if the lowering stuff changes in the future. Differential Revision: http://reviews.llvm.org/D4292 llvm-svn: 211892
* [x86] Teach the target-specific combining how to aggressively foldChandler Carruth2014-06-271-0/+90
| | | | | | | | | | | | | | | | | | half-shuffles, even looking through intervening instructions in a chain. Summary: This doesn't happen to show up with any test cases I've found for the current shuffle lowering, but previous attempts would benefit from this and it seems generally useful. I've tested it directly using intrinsics, which also shows that it will work with hand vectorized code as well. Note that even though pshufd isn't directly used in these tests, it gets exercised because we combine some of the half shuffles into a pshufd first, and then merge them. Differential Revision: http://reviews.llvm.org/D4291 llvm-svn: 211890
* [x86] Teach the X86 backend to DAG-combine SSE2 shuffles that areChandler Carruth2014-06-271-1/+101
| | | | | | | | | | | | | | | | | trivially redundant. This fixes several cases in the new vector shuffle lowering algorithm which would generate redundant shuffle instructions for the sake of simplicity. I'm also deleting a testcase which was somewhat ridiculous. It was checking for a bug in 2007 about incorrectly transforming shuffles by looking for the string "-86" in the output of a pretty substantial function. This test case doesn't seem to have any value at this point. Differential Revision: http://reviews.llvm.org/D4240 llvm-svn: 211889
* [x86] Begin a significant overhaul of how vector lowering is done in theChandler Carruth2014-06-271-0/+1029
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | x86 backend. This sketches out a new code path for vector lowering, hidden behind an off-by-default flag while it is under development. The fundamental idea behind the new code path is to aggressively break down the problem space in ways that ease selecting the odd set of instructions available on x86, and carefully avoid scalarizing code even when forced to use older ISAs. Notably, this starts off restricting itself to SSE2 and implements the complete vector shuffle and blend space for 128-bit vectors in SSE2 without scalarizing. The plan is to layer on top of this ISA extensions where we can bail out of the complex SSE2 lowering and opt for a cheaper, specialized instruction (or set of instructions). It also needs to be generalized to AVX and AVX512 vector widths. Currently, this does a decent but not perfect job for SSE2. There are some specific shortcomings that I plan to address: - We need a peephole combine to fold together shuffles where possible. There are cases where a previous shuffle could be modified slightly to arrange for elements to be in the correct position and a later shuffle eliminated. Doing this eagerly added quite a bit of complexity, and so my plan is to combine away these redundancies afterward. - There are a lot more clever ways to use unpck and pack that need to be added. This is essential for real world shuffles as it turns out... Once SSE2 is polished a bit I should be able to get interesting numbers on performance improvements on benchmarks conducive to vectorization. All of this will be off by default until it is functionally equivalent of course. Differential Revision: http://reviews.llvm.org/D4225 llvm-svn: 211888
* Remove the caching of the target machine from SystemZTargetLowering.Eric Christopher2014-06-272-21/+33
| | | | | | Update all callers and uses accordingly. llvm-svn: 211880
* Remove target machine caching from SystemZInstrInfo andEric Christopher2014-06-275-20/+18
| | | | | | | | SystemZRegisterInfo and replace it with the subtarget as that's all they needed in the first place. Update all uses and calls accordingly. llvm-svn: 211877
* Have SystemZSelectionDAGInfo constructor take a DataLayout ratherEric Christopher2014-06-273-6/+4
| | | | | | | than a target machine since it doesn't need anything past the DataLayout. llvm-svn: 211870
* Rename getX86ConditonCode -> getX86ConditionCodeCraig Topper2014-06-271-5/+5
| | | | llvm-svn: 211869
* Have MipsSelectionDAGInfo constructor take a DataLayout ratherEric Christopher2014-06-273-4/+4
| | | | | | | than a target machine since it doesn't need anything past the DataLayout. llvm-svn: 211863
* Move NVPTX subtarget dependent variables from the target machineEric Christopher2014-06-275-49/+70
| | | | | | to the subtarget. llvm-svn: 211860
* Use the target lowering we can get off of the DAG rather than offEric Christopher2014-06-271-1/+1
| | | | | | of the cached target machine. llvm-svn: 211858
* Fix missing newline and simplify debug printing.Matt Arsenault2014-06-271-5/+5
| | | | llvm-svn: 211850
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