summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* typo; NFCSanjay Patel2015-03-311-1/+1
| | | | llvm-svn: 233761
* [PowerPC] Don't use a vector preferred memory type at -O0Hal Finkel2015-03-311-15/+17
| | | | | | | | | | | | Even at -O0, we fall back to SDAG when we hit intrinsics, and if the intrinsic is a memset/memcpy/etc. we might normally use vector types. At -O0, this is probably not a good idea (because, if there is a bug in the lowering code, there would be no good way to turn it off). At -O0, only use scalar preferred types. Related to PR22754. llvm-svn: 233755
* [AArch64] Enable the codegenprepare optimization that promotes operation to formQuentin Colombet2015-03-312-0/+56
| | | | | | | | | | extended loads. Implement the related target lowering hook so that the optimization has a better estimation of the cost of an extension. rdar://problem/19267165 llvm-svn: 233753
* [Hexagon] Avoid an unused variable warning when assertions are offSimon Atanasyan2015-03-311-0/+1
| | | | | | No functional changes. llvm-svn: 233740
* [SystemZ] Address review comments for r233689Ulrich Weigand2015-03-311-4/+5
| | | | | | | | | | Change lowerCTPOP to: - Gracefully handle a known-zero input value - Simplify computation of significant bit size Thanks to Jay Foad for the review! llvm-svn: 233736
* [X86, AVX] fix zero-extending integer operand load patterns to use integer ↵Sanjay Patel2015-03-311-8/+9
| | | | | | | | | instructions This is a follow-on to r233704 and another partial fix for PR22685: https://llvm.org/bugs/show_bug.cgi?id=22685 llvm-svn: 233724
* [X86, AVX] try to lowerVectorShuffleAsElementInsertion() for all 256-bit ↵Sanjay Patel2015-03-311-18/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | vector sub-types I suggested this change in D7898 (http://llvm.org/viewvc/llvm-project?view=revision&revision=231354) It improves the v4i64 case although not optimally. This AVX codegen: vmovq {{.*#+}} xmm0 = mem[0],zero vxorpd %ymm1, %ymm1, %ymm1 vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] Becomes: vmovsd {{.*#+}} xmm0 = mem[0],zero Unfortunately, this doesn't completely solve PR22685. There are still at least 2 problems under here: We're not handling v32i8 / v16i16. We're not getting the FP / int domains right for instruction selection. But since this patch alone appears to do no harm, reduces code duplication, and helps v4i64, I'm submitting this patch ahead of fixing the above. Differential Revision: http://reviews.llvm.org/D8341 llvm-svn: 233704
* [SystemZ] Add Analysis to required_libraries (fall-out from r233688)Ulrich Weigand2015-03-311-1/+1
| | | | | | Should fix build failures with cmake builds llvm-svn: 233700
* Expand MUX instructions early on HexagonKrzysztof Parzyszek2015-03-315-10/+1371
| | | | | | This time with all files included. llvm-svn: 233696
* Revert 233694. Weak SVN-fu.Krzysztof Parzyszek2015-03-314-24/+10
| | | | llvm-svn: 233695
* Expand MUX instructions early on HexagonKrzysztof Parzyszek2015-03-314-10/+24
| | | | llvm-svn: 233694
* [AArch64] Add v8.1a "Rounding Double Multiply Add/Subtract" extensionVladimir Sukharev2015-03-312-0/+221
| | | | | | | | | | Reviewers: t.p.northover, jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8502 llvm-svn: 233693
* [SystemZ] Support RISBGN instruction on zEC12Ulrich Weigand2015-03-316-17/+48
| | | | | | | | | | | | | | So far, we do not yet support any instruction specific to zEC12. Most of the facilities added with zEC12 are indeed not very useful to compiler code generation, but there is one exception: the miscellaneous-extensions facility provides the RISBGN instruction, which is a variant of RISBG that does not set the condition code. Add support for this facility, MC support for RISBGN, and CodeGen support for prefering RISBGN over RISBG on zEC12, unless we can actually make use of the condition code set by RISBG. llvm-svn: 233690
* [SystemZ] Use POPCNT instruction on z196Ulrich Weigand2015-03-319-6/+85
| | | | | | | | | | We already exploit a number of instructions specific to z196, but not yet POPCNT. Add support for the population-count facility, MC support for the POPCNT instruction, CodeGen support for using POPCNT, and implement the getPopcntSupport TargetTransformInfo hook. llvm-svn: 233689
* [SystemZ] Provide basic TargetTransformInfo implementationUlrich Weigand2015-03-317-0/+320
| | | | | | | | | | | | This hooks up the TargetTransformInfo machinery for SystemZ, and provides an implementation of getIntImmCost. In addition, the patch adds the isLegalICmpImmediate and isLegalAddImmediate TargetLowering overrides, and updates a couple of test cases where we now generate slightly better code. llvm-svn: 233688
* Fix the operand encoding in the test instruction.Rafael Espindola2015-03-311-4/+4
| | | | | | Fixes pr22995. llvm-svn: 233686
* [PowerPC] Remove TargetMachine CPU auto-detectionUlrich Weigand2015-03-311-6/+0
| | | | | | As was done for X86 in r206094. llvm-svn: 233684
* [X86] Generate MOVNT for all vector types.Ahmed Bougacha2015-03-311-2/+19
| | | | | | | | We used to miss non-Q YMM integer vectors, and, non-Q/D XMM integer vectors. While there, change the v4i32 patterns to prefer MOVNTDQ. llvm-svn: 233668
* [bpf] mark mov instructions as ReMaterializableAlexei Starovoitov2015-03-311-2/+5
| | | | | | loading immediate into register is cheap, so take advantage of remat. llvm-svn: 233666
* [AArch64] Fix poor codegen for add immediate.Quentin Colombet2015-03-311-0/+2
| | | | | | | We used to match the register variant before the immediate when the register argument could be implicitly zero-extended. llvm-svn: 233653
* Replace the MCSubtargetInfo parameter with a Triple when creatingEric Christopher2015-03-3114-44/+43
| | | | | | | an MCInstPrinter. Update all callers and use where we wanted a Triple previously. llvm-svn: 233648
* Transfer implicit operands when expanding the RET_ReallyLR pseudo instruction.Juergen Ributzka2015-03-301-3/+6
| | | | | | | | | | | | When we expand the RET_ReallyLR pseudo instruction we also need to transfer the implicit operands. The return register is an implicit operand and without it the liveness calculation generates an incorrect live-out set for the patchpoint. This fixes rdar://problem/19068476. llvm-svn: 233635
* [bpf] add support for bswap instructionsAlexei Starovoitov2015-03-302-1/+27
| | | | | | | BPF has cpu_to_be and cpu_to_le instructions. For now assume little endian and generate cpu_to_be for ISD::BSWAP. llvm-svn: 233620
* [bpf] fix buildAlexei Starovoitov2015-03-301-2/+2
| | | | | | | fix build broken due to r233599. Would still need to switch to MDLocation long term. llvm-svn: 233619
* Remove unused MCSubtargetInfo argument from the X86 MCInstPrinter ctors.Eric Christopher2015-03-302-2/+2
| | | | llvm-svn: 233614
* Remove unused MCSubtargetInfo argument from the Sparc MCInstPrinter ctors.Eric Christopher2015-03-302-6/+4
| | | | llvm-svn: 233612
* Remove unused MCSubtargetInfo argument from the NVPTX MCInstPrinter ctors.Eric Christopher2015-03-303-6/+4
| | | | llvm-svn: 233611
* Remove unused MCSubtargetInfo argument from the ARM MCInstPrinter ctors.Eric Christopher2015-03-303-4/+3
| | | | llvm-svn: 233609
* Remove unused MCSubtargetInfo argument from the AArch64 MCInstPrinter ctors.Eric Christopher2015-03-303-10/+7
| | | | llvm-svn: 233608
* Remove unused Target argument from MCInstPrinter ctor functions.Eric Christopher2015-03-3014-34/+22
| | | | llvm-svn: 233607
* MC: For variable symbols, maintain MCSymbol::Section as a cache.Peter Collingbourne2015-03-301-1/+0
| | | | | | | | | | | This fixes the visibility of symbols in certain edge cases involving aliases with multiple levels of indirection. Fixes PR19582. Differential Revision: http://reviews.llvm.org/D8586 llvm-svn: 233595
* [NVPTX] Associate a minimum PTX version for each SM architectureJustin Holewinski2015-03-301-9/+5
| | | | | | | | | | When a new SM architecture is introduced, it is only supported by the current PTX version and later. Make sure we are using at least the minimum PTX version for the target architecture. This also removes support for PTX ISA < 3.2. llvm-svn: 233583
* CodeGen: Use the new DebugLoc API, NFCDuncan P. N. Exon Smith2015-03-302-8/+4
| | | | | | Update lib/CodeGen (and lib/Target) to use the new `DebugLoc` API. llvm-svn: 233582
* [NVPTX] Add options for PTX 4.1/4.2 and SM 3.2/3.7/5.2/5.3Justin Holewinski2015-03-301-0/+16
| | | | llvm-svn: 233575
* Remove more superfluous .str() and replace std::string concatenation with Twine.Yaron Keren2015-03-309-32/+33
| | | | | | Following r233392, http://llvm.org/viewvc/llvm-project?rev=233392&view=rev. llvm-svn: 233555
* more space; NFCSanjay Patel2015-03-301-1/+1
| | | | llvm-svn: 233554
* [SystemZ] Fix LLVM crash on unoptimized codeUlrich Weigand2015-03-301-0/+2
| | | | | | | | | | | | | | Compiling the following function with -O0 would crash, since LLVM would hit an assertion in getTestUnderMaskCond: int test(unsigned long x) { return x >= 0 && x <= 15; } Fixed by detecting the case in the caller of getTestUnderMaskCond. llvm-svn: 233541
* [SystemZ] Remove TargetMachine CPU auto-detectionUlrich Weigand2015-03-301-5/+0
| | | | | | As was done for X86 in r206094. llvm-svn: 233540
* [mips] Support 9-bit offsets for the 'R' inline assembly memory constraint.Daniel Sanders2015-03-301-1/+14
| | | | | | | | | | | | | | | | | | | Summary: The 'R' constraint is actually supposed to be much more complicated than this and is defined in terms of whether it will cause macro expansion in the assembler. 'R' is getting less useful due to architecture changes and ought to be replaced by other constraints. We therefore implement 9-bit offsets which will work for all subtargets and all instructions. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8440 llvm-svn: 233537
* AVX-512: blank lines, duplicated tests, no functional changesElena Demikhovsky2015-03-301-21/+27
| | | | | | see comments http://reviews.llvm.org/D6835 llvm-svn: 233528
* AVX-512: added intrinsics for VPAND, VPOR and VPXORElena Demikhovsky2015-03-301-0/+6
| | | | | | by Asaf Badouh (asaf.badouh@intel.com) llvm-svn: 233525
* [X86] Remove FeatureAES for 'corei7' CPU. 'corei7' should match 'nehalem' ↵Craig Topper2015-03-301-11/+9
| | | | | | which doesn't have AES. Having AES and not PCLMUL makes 'corei7' halfway between Nehalem and Westmere. llvm-svn: 233517
* AVX-512: Fixed the "commutative" property flag in VPANDN instructionElena Demikhovsky2015-03-291-1/+1
| | | | | | By Asaf Badouh (asaf.badouh@intel.com) llvm-svn: 233489
* Delete MCInstPrinter::AvailableFeatures.Akira Hatanaka2015-03-281-3/+1
| | | | | | | | | All the ports have been fixed to read the feature bits from the subtarget passed to the print methods. Also, delete the call to setAvailableFeatures in the constructor of NVPTX's instprinter as the instprinter wasn't using the feature bits anywhere. llvm-svn: 233486
* [X86] Read the feature bits from the subtarget that is passed to printInstAkira Hatanaka2015-03-282-5/+2
| | | | | | instead of from MCInstPrinter::AvailableFeatures. llvm-svn: 233485
* [PowerPC] Add asm parser support for bitmask forms of rotate-and-mask ↵Hal Finkel2015-03-284-31/+95
| | | | | | | | | | | | | | | instructions The asm syntax for the 32-bit rotate-and-mask instructions can take a 32-bit bitmask instead of an (mb, me) pair. This syntax is not specified in the Power ISA manual, but is accepted by GNU as, and is documented in IBM's Assembler Language Reference. The GNU Multiple Precision Arithmetic Library (gmp) contains assembly that uses this syntax. To implement this, I moved the isRunOfOnes utility function from PPCISelDAGToDAG.cpp to PPCMCTargetDesc.h. llvm-svn: 233483
* Partially revert the changes I made in r233473 to keep the code concise.Akira Hatanaka2015-03-281-137/+47
| | | | llvm-svn: 233474
* clang-format X86ATTInstPrinter.{h,cpp} before I make changes to these files.Akira Hatanaka2015-03-282-76/+156
| | | | llvm-svn: 233473
* [SparcInstPrinter] Use the subtarget that is passed to the print functionAkira Hatanaka2015-03-283-34/+47
| | | | | | | | | | | instead of the one passed to the constructor. Unfortunately, I don't have a test case for this change. In order to test my change, I will have to run the code after line 90 in printSparcAliasInstr. I couldn't make that happen because printAliasInstr would always handle the printing of fcmp instructions that the code after line 90 is supposed to handle. llvm-svn: 233471
* [ARM] Enable changing instprinter's behavior based on the per-functionAkira Hatanaka2015-03-273-141/+276
| | | | | | subtarget. llvm-svn: 233451
OpenPOWER on IntegriCloud