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* Move emitInlineAsmEnd to the AsmPrinter interface.Rafael Espindola2014-01-243-17/+19
| | | | | | | | There is no inline asm in a .s file. Therefore, there should be no logic to handle it in the streamer. Inline asm only exists in bitcode files, so the logic can live in the (long misnamed) AsmPrinter class. llvm-svn: 200011
* [AArch64 NEON] Fix a bug in implementing register copy bwtween FPR16.Kevin Qin2014-01-241-2/+2
| | | | llvm-svn: 199978
* [SparcV9] Add support for JIT in Sparc64.Venkatraman Govindaraju2014-01-245-45/+189
| | | | | | With this change, all supported tests in test/ExecutionEngine pass in sparcv9. llvm-svn: 199977
* [X86] Prevent the creation of redundant ops for sadd and ssub with overflow.Juergen Ributzka2014-01-241-2/+17
| | | | | | | | | | | | | This commit teaches the X86 backend to create the same X86 instructions when it lowers an sadd/ssub with overflow intrinsic and a conditional branch that uses that overflow result. This allows SelectionDAG to recognize and remove one of the redundant operations. This fixes <rdar://problem/15874016> and <rdar://problem/15661073>. Reviewed by Nadav llvm-svn: 199976
* Implement atomicrmw operations in 32 and 64 bits for SPARCv9.Jakob Stoklund Olesen2014-01-243-12/+180
| | | | | | These all use the compare-and-swap CASA/CASXA instructions. llvm-svn: 199975
* [Sparc] Correct quad register list in the asm parser.Venkatraman Govindaraju2014-01-241-1/+1
| | | | | | Add test cases to check parsing of v9 double registers and their aliased quad registers. llvm-svn: 199974
* InitToTextSection is redundant with InitSections. Remove it.Rafael Espindola2014-01-231-1/+1
| | | | llvm-svn: 199955
* Update the X86 assembler for .intel_syntax to produce an error for invalid baseKevin Enderby2014-01-231-32/+48
| | | | | | | | | registers in memory addresses that do not match the index register. As it does for .att_syntax. rdar://15887380 llvm-svn: 199948
* Update the X86 assembler for .intel_syntax to produce an error for invalidKevin Enderby2014-01-231-3/+11
| | | | | | | | | | | scale factors in memory addresses. As it does for .att_syntax. It was producing: Assertion failed: (((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) && "Invalid scale!"), function CreateMem, file /Volumes/SandBox/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp, line 1133. rdar://14967214 llvm-svn: 199942
* Fix out of bounds access to the double regs array. Given theEric Christopher2014-01-231-1/+1
| | | | | | | code this looks correct, but could use review. The previous was definitely not correct. llvm-svn: 199940
* Add a few missing cases from r199933. Testcase coming shortly.Lang Hames2014-01-231-0/+8
| | | | llvm-svn: 199938
* Replace vfmaddxx213 instructions with their 231-type equivalents in accumulatorLang Hames2014-01-233-3/+107
| | | | | | | loops. Writing back to the accumulator (231-type) allows the coalescer to eliminate an extra copy. llvm-svn: 199933
* [Thumbv8] Fix the value of BLXOperandIndex of isV8EligibleForITWeiming Zhao2014-01-232-4/+3
| | | | | | | | | Originally, BLX was passed as operand #0 in MachineInstr and as operand #2 in MCInst. But now, it's operand #2 in both cases. This patch also removes unnecessary FileCheck in the test case added by r199127. llvm-svn: 199928
* Add target analysis passes to the codegen pipeline for MCJIT.Juergen Ributzka2014-01-231-0/+4
| | | | | | | | | | | This patch adds the target analysis passes (usually TargetTransformInfo) to the codgen pipeline. We also expose now the AddAnalysisPasses method through the C API, because the optimizer passes would also benefit from better target-specific cost models. Reviewed by Andrew Kaylor llvm-svn: 199926
* [AArch64] Added vselect patterns with float and double typesAna Pazos2014-01-231-0/+4
| | | | llvm-svn: 199925
* R600: Remove successive JUMP in AnalyzeBranch when AllowModify is trueTom Stellard2014-01-231-1/+7
| | | | | | | | | | | | This fixes a crash in the OpenCV OpenCL test suite. There is no lit test for this, because the test would be very large and could easily be invalidated by changes to the scheduler or other parts of the compiler. Patch by: Vincent Lejeune llvm-svn: 199919
* R600: Disable the BFE patternTom Stellard2014-01-232-1/+10
| | | | | | | | | | This pattern uses an SDNodeXForm, which isn't being emitted for some reason. I can get it to work by attaching the PatLeaf that has the XForm to the argument in the output pattern, but this results in an immediate being used in a register operand, which the backend can't handle yet. llvm-svn: 199918
* R600: Correctly handle vertex fetch clauses the precede ENDIFsTom Stellard2014-01-231-0/+1
| | | | | | | | The control flow finalizer would sometimes use an ALU_POP_AFTER instruction before the vetex fetch clause instead of using a POP instruction after it. llvm-svn: 199917
* R600: Unconditionally unroll loops that contain GEPs with alloca pointersTom Stellard2014-01-231-0/+29
| | | | | | | | | | | | Implement the getUnrollingPreferences() function for AMDGPUTargetTransformInfo so that loops that do address calculations on pointers derived from alloca are unconditionally unrolled. Unrolling these loops makes it more likely that SROA will be able to eliminate the allocas, which is a big win for R600 since memory allocated by alloca (private memory) is really slow. llvm-svn: 199916
* R600: Recommit 199842: Add work-around for the CF stack entry HW bugTom Stellard2014-01-235-7/+63
| | | | | | | | | | | | | | | | | | The unit test is now disabled on non-asserts builds. The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE, CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of sub-entries on the stack is greater than or equal to the stack entry size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is present when number of sub-entries module 8 is either 7 or 0) We choose to be conservative and always apply the work-around when the number of sub-enries is greater than or equal to the stack entry size, so that we can safely over-allocate the stack when we are unsure of the stack allocation rules. reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199905
* AVX-512: added VPERM2D VPERM2Q VPERM2PS VPERM2PD instructions,Elena Demikhovsky2014-01-235-152/+165
| | | | | | they give better sequences than VPERMI llvm-svn: 199893
* ARM: use litpools for normal i32 imms when compiling minsize.Tim Northover2014-01-233-11/+13
| | | | | | | | | With constant-sharing, litpool loads consume 4 + N*2 bytes of code, but movw/movt pairs consume 8*N. This means litpools are better than movw/movt even with just one use. Other materialisation strategies can still be better though, so the logic is a little odd. llvm-svn: 199891
* [mips][sched] Split IIStore into II_S[BHWD], II_S[WD][LR], and II_SAVEDaniel Sanders2014-01-234-23/+39
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199876
* Add a variable to track whether or not we've used a unique section,Eric Christopher2014-01-2310-23/+22
| | | | | | | | | | | | e.g. linkonce, to TargetMachine and set it when we've done so for ELF targets currently. This involved making TargetMachine non-const in a TLOF use and propagating that change around - I'm open to other ideas. This will be used in a future commit to handle emitting debug information with ranges. llvm-svn: 199871
* fix some spell mistakes around 'ConcatVector' and 'ShuffleVector' in AArch64 ↵Kevin Qin2014-01-232-5/+5
| | | | | | backend. llvm-svn: 199858
* X86Disassembler.cpp: Fix @param introduced in r199804. [-Wdocumentation]NAKAMURA Takumi2014-01-231-1/+0
| | | | llvm-svn: 199855
* [Mips] formatting through clang-formatJack Carter2014-01-221-10/+10
| | | | llvm-svn: 199853
* [Mips] TargetStreamer Support for .set mips16.Jack Carter2014-01-223-3/+49
| | | | | | | | | | This patch updates .set mips16 support which affects the ELF ABI and its flags. In addition the patch uses a common interface for both the MipsTargetSteamer and MipsObjectStreamer that the assembler uses for both ELF and ASCII output for these directives. llvm-svn: 199851
* Revert "R600: Add work-around for the CF stack entry HW bug"Tom Stellard2014-01-225-63/+7
| | | | | | | | | This reverts commit 35b8331cad6eb512a2506adbc394201181da94ba. The -debug-only flag for llc doesn't appear to be available in all build configurations. llvm-svn: 199845
* R600: Add work-around for the CF stack entry HW bugTom Stellard2014-01-225-7/+63
| | | | | | | | | | | | | | | | The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE, CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of sub-entries on the stack is greater than or equal to the stack entry size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is present when number of sub-entries module 8 is either 7 or 0) We choose to be conservative and always apply the work-around when the number of sub-enries is greater than or equal to the stack entry size, so that we can safely over-allocate the stack when we are unsure of the stack allocation rules. reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199842
* R600: Add some missing CF instruction definitions to the .td files.Tom Stellard2014-01-221-0/+7
| | | | | reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199841
* R600: Refactor stack size calculationTom Stellard2014-01-223-36/+157
| | | | | reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199840
* R600: CF_PUSH is the same on Evergreen and CaymanTom Stellard2014-01-222-4/+5
| | | | | reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199839
* R600: Add wavefront size property to the subtargets v2Tom Stellard2014-01-224-12/+33
| | | | | | | | v2: - Initialize wavefront size to 0 reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199838
* R600: Add stack size to .AMDGPUcsdata sectionTom Stellard2014-01-221-4/+10
| | | | | reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199837
* Fix pr18515.Rafael Espindola2014-01-222-14/+18
| | | | | | | | | | | | | My understanding (from reading just the llvm code) is that * most ppc cpus have a "sync n" instruction and an msync alias that is "sync 0". * "book e" cpus instead have a msync instruction and not the more general "sync n" This patch reflects that in the .td files, allowing a single codepath for asm ond obj streamer and incidentelly fixes a crash when EmitRawText was called on a obj streamer. llvm-svn: 199832
* R600: MOVA is vector onlyTom Stellard2014-01-221-1/+1
| | | | llvm-svn: 199827
* R600: Take alignment into account when calculating the stack offsetTom Stellard2014-01-221-4/+11
| | | | llvm-svn: 199826
* R600: Add support for global addresses with constant initializersTom Stellard2014-01-223-15/+108
| | | | llvm-svn: 199825
* R600: Begin private memory at the second GPR.Tom Stellard2014-01-221-1/+4
| | | | | | | This way private memory does not over-write work group information stored in GPRs 0 and 1. llvm-svn: 199824
* R600/SI: Add support for i8 and i16 private loads/storesTom Stellard2014-01-224-11/+141
| | | | llvm-svn: 199823
* Fix inline assembly that switches between ARM and Thumb modesGreg Fitzgerald2014-01-221-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch restores the ARM mode if the user's inline assembly does not. In the object streamer, it ensures that instructions following the inline assembly are encoded correctly and that correct mapping symbols are emitted. For the asm streamer, it emits a .arm or .thumb directive. This patch does not ensure that the inline assembly contains the ADR instruction to switch modes at runtime. The problem we need to solve is code like this: int foo(int a, int b) { int r = a + b; asm volatile( ".align 2 \n" ".arm \n" "add r0,r0,r0 \n" : : "r"(r)); return r+1; } If we compile this function in thumb mode then the inline assembly will switch to arm mode. We need to make sure that we switch back to thumb mode after emitting the inline assembly or we will incorrectly encode the instructions that follow (i.e. the assembly instructions for return r+1). Based on patch by David Peixotto Change-Id: Ib57f6d2d78a22afad5de8693fba6230ff56ba48b llvm-svn: 199818
* Remove param doxygen comment for non-existing parameter.Benjamin Kramer2014-01-221-1/+0
| | | | | | Found by -Wdocumentation. llvm-svn: 199814
* [x86] Silence unused diReg variable warning in non-asserting buildsDavid Woodhouse2014-01-221-4/+3
| | | | llvm-svn: 199812
* [x86] Fix uninitialized variable warning in translate{Src,Dst}IndexDavid Woodhouse2014-01-221-2/+6
| | | | llvm-svn: 199811
* [x86] Remove now-unused isSrcOp() and isDstOp() from X86AsmParserDavid Woodhouse2014-01-221-30/+0
| | | | llvm-svn: 199810
* [x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)David Woodhouse2014-01-222-13/+17
| | | | llvm-svn: 199809
* [x86] Allow segment and address-size overrides for OUTS[BWLQ] (PR9385)David Woodhouse2014-01-222-13/+16
| | | | llvm-svn: 199808
* [x86] Allow segment and address-size overrides for MOVS[BWLQ] (PR9385)David Woodhouse2014-01-222-21/+34
| | | | llvm-svn: 199807
* ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)David Woodhouse2014-01-225-5/+80
| | | | llvm-svn: 199806
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