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* X86 cost model: Differentiate cost for vector shifts of constantsArnold Schwaighofer2013-04-041-0/+29
| | | | | | | | | | | | SSE2 has efficient support for shifts by a scalar. My previous change of making shifts expensive did not take this into account marking all shifts as expensive. This would prevent vectorization from happening where it is actually beneficial. With this change we differentiate between shifts of constants and other shifts. radar://13576547 llvm-svn: 178808
* CostModel: Add parameter to instruction cost to further classify operand valuesArnold Schwaighofer2013-04-042-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On certain architectures we can support efficient vectorized version of instructions if the operand value is uniform (splat) or a constant scalar. An example of this is a vector shift on x86. We can efficiently support for (i = 0 ; i < ; i += 4) w[0:3] = v[0:3] << <2, 2, 2, 2> but not for (i = 0; i < ; i += 4) w[0:3] = v[0:3] << x[0:3] This patch adds a parameter to getArithmeticInstrCost to further qualify operand values as uniform or uniform constant. Targets can then choose to return a different cost for instructions with such operand values. A follow-up commit will test this feature on x86. radar://13576547 llvm-svn: 178807
* Rename the current PPC BCL definition to BCLalwaysHal Finkel2013-04-043-5/+5
| | | | | | | | | | | | BCL is normally a conditional branch-and-link instruction, but has an unconditional form (which is used in the SjLj code, for example). To make clear that this BCL instruction definition is specifically the special unconditional form (which does not meaningfully take a condition-register input), rename it to BCLalways. No functionality change intended. llvm-svn: 178803
* PPC: Improve code generation for mixed-precision reciprocal sqrtHal Finkel2013-04-041-0/+27
| | | | | | | | The DAGCombine logic that recognized a/sqrt(b) and transformed it into a multiplication by the reciprocal sqrt did not handle cases where the sqrt and the division were separated by an fpext or fptrunc. llvm-svn: 178801
* Hexagon: Expand br_cc.Jyotsna Verma2013-04-041-0/+2
| | | | | | | | | | | | | It fixes following tests for Hexagon: CodeGen/Generic/2003-07-29-BadConstSbyte.ll CodeGen/Generic/2005-10-21-longlonggtu.ll CodeGen/Generic/2009-04-28-i128-cmp-crash.ll CodeGen/Generic/MachineBranchProb.ll CodeGen/Generic/builtin-expect.ll CodeGen/Generic/pr12507.ll llvm-svn: 178794
* [XCore] Add bru instruction.Richard Osborne2013-04-041-0/+3
| | | | llvm-svn: 178783
* [XCore] The RRegs register class is a superset of GRRegs.Richard Osborne2013-04-044-34/+46
| | | | | | | | | | At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. llvm-svn: 178782
* Avoid high-latency false CPSR dependencies even for tMOVSi.Jakob Stoklund Olesen2013-04-041-46/+103
| | | | | | | | | | | | | | | | | The Thumb2SizeReduction pass avoids false CPSR dependencies, except it still aggressively creates tMOVi8 instructions because they are so common. Avoid creating false CPSR dependencies even for tMOVi8 instructions when the the CPSR flags are known to have high latency. This allows integer computation to overlap floating point computations. Also process blocks in a reverse post-order and propagate high-latency flags to successors. <rdar://problem/13468102> llvm-svn: 178773
* R600: Use a mask for offsets when encoding instructionsVincent Lejeune2013-04-041-2/+5
| | | | llvm-svn: 178763
* R600: Fix wrong address when substituting ENDIFVincent Lejeune2013-04-041-1/+1
| | | | llvm-svn: 178762
* R600: Take export into account when computing cf addressVincent Lejeune2013-04-041-0/+4
| | | | llvm-svn: 178761
* Add SPARC v9 support for select on 64-bit compares.Jakob Stoklund Olesen2013-04-044-5/+35
| | | | | | | | | | | This requires v9 cmov instructions using the %xcc flags instead of the %icc flags. Still missing: - Select floats on %xcc flags. - Select i64 on %fcc flags. llvm-svn: 178737
* X86 cost model: Vector shifts are expensive in most casesArnold Schwaighofer2013-04-031-0/+42
| | | | | | | | | | | | | | The default logic does not correctly identify costs of casts because they are marked as custom on x86. For some cases, where the shift amount is a scalar we would be able to generate better code. Unfortunately, when this is the case the value (the splat) will get hoisted out of the loop, thereby making it invisible to ISel. radar://13130673 radar://13537826 llvm-svn: 178703
* R600: Fix last ALU of a clause being emitted in a separate clauseVincent Lejeune2013-04-031-2/+2
| | | | llvm-svn: 178675
* Cleanup PPC reciprocal-estimate functionalityHal Finkel2013-04-032-61/+47
| | | | | | | Incorporating review feedback from Bill Schmidt on r178617. No functionality change intended. llvm-svn: 178672
* R600: Factorize maximum alu per clause in a single locationVincent Lejeune2013-04-034-2/+6
| | | | llvm-svn: 178667
* R600: Simplify data structure and add DEBUG to R600ControlFlowFinalizerVincent Lejeune2013-04-031-20/+21
| | | | llvm-svn: 178665
* R600: Consider KILLGT as an ALU instructionVincent Lejeune2013-04-032-3/+4
| | | | | | | Mesa does not override llvm behavior wrt KILLGT anymore so llvm has to handle KILLGT on its own. llvm-svn: 178664
* PPC: Enable FRES and FRSQRTE on the default PPC64 descriptionHal Finkel2013-04-031-1/+2
| | | | | | | I discussed this with Bill Schmidt on IRC, and it was decided that this is a safe and reasonable default. llvm-svn: 178659
* PPC: Add a FIXME regarding the non-working fma+fneg Altivec patternHal Finkel2013-04-031-0/+2
| | | | llvm-svn: 178658
* Remove some obsolete PowerPC/README entriesHal Finkel2013-04-031-20/+0
| | | | llvm-svn: 178657
* More direct types in PowerPC AltiVec intrinsics.Ulrich Weigand2013-04-031-47/+29
| | | | | | | | | | This patch follows up on work done by Bill Schmidt in r178277, and replaces most of the remaining uses of VRRC in ISEL DAG patterns. The resulting .inc files are identical except for comments, so no change in code generation is expected. llvm-svn: 178656
* Fix PR15632: No support for ppcf128 floating-point remainder on PowerPC.Bill Schmidt2013-04-031-0/+1
| | | | | | | | For this we need to use a libcall. Previously LLVM didn't implement libcall support for frem, so I've added it in the usual straightforward manner. A test case from the bug report is included. llvm-svn: 178639
* AArch64: implement ETMv4 trace system registers.Tim Northover2013-04-032-0/+432
| | | | llvm-svn: 178637
* Fix SRet for thiscall in i686-pc-win32Timur Iskhodzhanov2013-04-031-2/+2
| | | | llvm-svn: 178634
* AArch64: switch patterns to be type-based rather than RegClass-basedTim Northover2013-04-031-503/+492
| | | | | | | It's a bit of churn in the blame log, but I think there are real benefits to the newer system so I'm making the change in one go. llvm-svn: 178633
* Add 64-bit compare + branch for SPARC v9.Jakob Stoklund Olesen2013-04-035-5/+34
| | | | | | | | | | The same compare instruction is used for 32-bit and 64-bit compares. It sets two different sets of flags: icc and xcc. This patch adds a conditional branch instruction using the xcc flags for 64-bit compares. llvm-svn: 178621
* Remove some unsupported-feature comments from PPC.tdHal Finkel2013-04-031-3/+0
| | | | | | These refer to the reciprocal estimate support recently committed. llvm-svn: 178618
* Use PPC reciprocal estimates with Newton iteration in fast-math modeHal Finkel2013-04-037-30/+321
| | | | | | | | | | | | | | | | | | | When unsafe FP math operations are enabled, we can use the fre[s] and frsqrte[s] instructions, which generate reciprocal (sqrt) estimates, together with some Newton iteration, in order to quickly generate floating-point division and sqrt results. All of these instructions are separately optional, and so each has its own feature flag (except for the Altivec instructions, which are covered under the existing Altivec flag). Doing this is not only faster than using the IEEE-compliant fdiv/fsqrt instructions, but allows these computations to be pipelined with other computations in order to hide their overall latency. I've also added a couple of missing fnmsub patterns which turned out to be missing (but are necessary for good code generation of the Newton iterations). Altivec needs a similar fix, but that will probably be more complicated because fneg is expanded for Altivec's v4f32. llvm-svn: 178617
* Formatting.Eric Christopher2013-04-021-2/+1
| | | | llvm-svn: 178589
* [mips] Small update to the implementation of eh.return for Mips.Akira Hatanaka2013-04-021-0/+4
| | | | | | | | | | This patch initializes t9 to the handler address, but only if the relocation model is pic. This handles the case where handler to which eh.return jumps points to the start of the function. Patch by Sasa Stankovic. llvm-svn: 178588
* [mips] Expand pseudo multiply/divide instructions in MipsCodeEmitter.cpp.Akira Hatanaka2013-04-021-0/+36
| | | | | | | | | | This patch fixes the following two tests which have been failing on llvm-mips-linux builder since r178403: LLVM :: Analysis/Profiling/load-branch-weights-ifs.ll LLVM :: Analysis/Profiling/load-branch-weights-loops.ll llvm-svn: 178584
* [ms-inline asm] Add support for parsing variables with namespace aliasChad Rosier2013-04-021-0/+54
| | | | | | | | | | | | | qualifiers. This patch only adds support for parsing these identifiers in the X86AsmParser. The front-end interface isn't capable of looking up these identifiers at this point in time. The end result is the compiler now errors during object file emission, rather than at parse time. Test case coming shortly. Part of rdar://13499009 and PR13340 llvm-svn: 178566
* Fix PR15630: Replace faulty stdcx. with stwcx.Bill Schmidt2013-04-021-1/+1
| | | | | | | | | | When doing a partword atomic operation, a lwarx was being paired with a stdcx. instead of a stwcx. when compiling for a 64-bit target. The target has nothing to do with it in this case; we always need a stwcx. Thanks to Kai Nacke for reporting the problem. llvm-svn: 178559
* [fast-isel] Use the correct API to disable FastLowerArguments for Win64.Chad Rosier2013-04-021-1/+1
| | | | llvm-svn: 178549
* [NVPTX] Fix a few style issues in NVVMReflectJustin Holewinski2013-04-021-72/+56
| | | | llvm-svn: 178536
* Add 64-bit load and store instructions.Jakob Stoklund Olesen2013-04-021-0/+68
| | | | | | There is only a few new instructions, the rest is handled with patterns. llvm-svn: 178528
* Basic 64-bit ALU operations.Jakob Stoklund Olesen2013-04-021-0/+38
| | | | | | | SPARC v9 extends all ALU instructions to 64 bits, so we simply need to add patterns to use them for both i32 and i64 values. llvm-svn: 178527
* Materialize 64-bit immediates.Jakob Stoklund Olesen2013-04-021-0/+88
| | | | | | | The last resort pattern produces 6 instructions, and there are still opportunities for materializing some immediates in fewer instructions. llvm-svn: 178526
* Add 64-bit shift instructions.Jakob Stoklund Olesen2013-04-023-0/+86
| | | | | | | | | | | SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right instructions are still usable as zero and sign extensions. This adds new F3_Sr and F3_Si instruction formats that probably should be used for the 32-bit shifts as well. They don't really encode an simm13 field. llvm-svn: 178525
* Add predicates for distinguishing 32-bit and 64-bit modes.Jakob Stoklund Olesen2013-04-021-0/+6
| | | | | | | | | | | The 'sparc' architecture produces 32-bit code while 'sparcv9' produces 64-bit code. It is also possible to run 32-bit code using SPARC v9 instructions with: llc -march=sparc -mattr=+v9 llvm-svn: 178524
* Add support for 64-bit calling convention.Jakob Stoklund Olesen2013-04-023-11/+115
| | | | | | | | | | | | This is far from complete, but it is enough to make it possible to write test cases using i64 arguments. Missing features: - Floating point arguments. - Receiving arguments on the stack. - Calls. llvm-svn: 178523
* Add an I64Regs register class for 64-bit registers.Jakob Stoklund Olesen2013-04-026-11/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | We are going to use the same registers for 32-bit and 64-bit values, but in two different register classes. The I64Regs register class has a larger spill size and alignment. The addition of an i64 register class confuses TableGen's type inference, so it is necessary to clarify the type of some immediates and the G0 register. In 64-bit mode, pointers are i64 and should use the I64Regs register class. Implement getPointerRegClass() to dynamically provide the pointer register class depending on the subtarget. Use ptr_rc and iPTR for memory operands. Finally, add the i64 type to the IntRegs register class. This register class is not used to hold i64 values, I64Regs is for that. The type is required to appease TableGen's type checking in output patterns like this: def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>; SPARC v9 uses the same ADDrr instruction for i32 and i64 additions, and TableGen doesn't know to check the type of register sub-classes. llvm-svn: 178522
* Fix typo in PPCISelLoweringHal Finkel2013-04-021-1/+1
| | | | | | Thanks to Bill Schmidt for finding this in review of r178480. llvm-svn: 178521
* The divide unit is not pipeline, but it is still buffered.Andrew Trick2013-04-022-4/+4
| | | | | | | | | | | | | | | | | | | | Buffered means a later divide may be executed out-of-order while a prior divide is sitting (buffered) in a reservation station. You can tell it's not pipelined, because operations that use it reserve it for more than one cycle: def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> { let Latency = 25; let ResourceCycles = [1, 10]; } We don't currently distinguish between an unpipeline operation and one that is split into multiple micro-ops requiring the same unit. Except that the later may have NumMicroOps > 1 if they also consume issue/dispatch resources. llvm-svn: 178519
* Target/R600: Fix CMake build to add missing files.NAKAMURA Takumi2013-04-011-0/+3
| | | | llvm-svn: 178508
* R600: Add support for native control flowVincent Lejeune2013-04-015-1/+386
| | | | llvm-svn: 178505
* R600/SI: Share code recording ShaderTypeAttribute between generationsVincent Lejeune2013-04-016-28/+60
| | | | llvm-svn: 178504
* R600: Emit CF_ALU and use true kcache register.Vincent Lejeune2013-04-016-10/+397
| | | | llvm-svn: 178503
* Fix a bad assert in PPCTargetLoweringHal Finkel2013-04-011-2/+2
| | | | llvm-svn: 178489
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