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* [SystemZ] Remove redundant frame MMOsRichard Sandiford2013-07-051-24/+4
| | | | | | | | | | This fixes foldMemoryOperandImpl() so that it doesn't create duplicated frame MMOs. I hadn't realized when writing r185434 that it was the caller's responsibility to add these. No behavioural change intended. llvm-svn: 185704
* [SystemZ] Enable the use of MVC for frame-to-frame spillsRichard Sandiford2013-07-051-10/+2
| | | | | | | | | | ...now that the problem that prompted the restriction has been fixed. The original spill-02.py was a compromise because at the time I couldn't find an example that actually failed without the two scavenging slots. The version included here did. llvm-svn: 185701
* [PowerPC] Add some special @got@tprel fixup casesUlrich Weigand2013-07-051-0/+20
| | | | | | | | | | | | | | | When a target@got@tprel or target@got@tprel@l symbol variant is used in a fixup_ppc_half16 (*not* fixup_ppc_half16ds) context, we currently fail, since the corresponding R_PPC64_GOT_TPREL16 / R_PPC64_GOT_TPREL16_LO relocation types do not exist. However, since such symbol variants resolve to GOT offsets which are always 4-aligned, we can simply instead use the _DS variants of the relocation types, which *do* exist. The same applies for the @got@dtprel variants. llvm-svn: 185700
* [SystemZ] Allocate a second register scavenging slotRichard Sandiford2013-07-051-2/+6
| | | | | | | | | | | | | This is another prerequisite for frame-to-frame MVC copies. I'll commit the patch that makes use of the slot separately. The downside of trying to test many corner cases with each of the available addressing modes is that a fair few tests need to account for the new frame layout. I do still think it's useful to have all these tests though, since it's something that wouldn't get much coverage otherwise. llvm-svn: 185698
* [SystemZ] Clean up register scavenging codeRichard Sandiford2013-07-054-57/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | SystemZ wants normal register scavenging slots, as close to the stack or frame pointer as possible. The only reason it was using custom code was because PrologEpilogInserter assumed an x86-like layout, where the frame pointer is at the opposite end of the frame from the stack pointer. This meant that when frame pointer elimination was disabled, the slots ended up being as close as possible to the incoming stack pointer, which is the opposite of what we want on SystemZ. This patch adds a new knob to say which layout is used and converts SystemZ to use target-independent scavenging slots. It's one of the pieces needed to support frame-to-frame MVCs, where two slots might be required. The ABI requires us to allocate 160 bytes for calls, so one approach would be to use that area as temporary spill space instead. It would need some surgery to make sure that the slot isn't live across a call though. I stuck to the "isFPCloseToIncomingSP - ..." style comment on the "do what the surrounding code does" principle. The FP case is already covered by several Systemz/frame-* tests, which fail without the PrologueEpilogueInserter change, so no new ones are needed. No behavioural change intended. llvm-svn: 185696
* [PowerPC] Support @tls in the asm parserUlrich Weigand2013-07-059-22/+70
| | | | | | | | | | | | | | | | | | This adds support for the last missing construct to parse TLS-related assembler code: add 3, 4, symbol@tls The ADD8TLS currently hard-codes the @tls into the assembler string. This cannot be handled by the asm parser, since @tls is parsed as a symbol variant. This patch changes ADD8TLS to have the @tls suffix printed as symbol variant on output too, which allows us to remove the isCodeGenOnly marker from ADD8TLS. This in turn means that we can add a AsmOperand to accept @tls marked symbols on input. As a side effect, this means that the fixup_ppc_tlsreg fixup type is no longer necessary and can be merged into fixup_ppc_nofixup. llvm-svn: 185692
* PR16490: fix a crash in ARMDAGToDAGISel::SelectInlineAsm.Joey Gouly2013-07-051-0/+6
| | | | | | | | | | | In the SelectionDAG immediate operands to inline asm are constructed as two separate operands. The first is a constant of value InlineAsm::Kind_Imm and the second is a constant with the value of the immediate. In ARMDAGToDAGISel::SelectInlineAsm, if we reach an operand of Kind_Imm we should skip over the next operand too. llvm-svn: 185688
* Use a OwningPtr instead of a manual delete.Rafael Espindola2013-07-041-5/+3
| | | | llvm-svn: 185673
* Fix leak. Should bring back the valgrind bot.Rafael Espindola2013-07-041-0/+1
| | | | llvm-svn: 185663
* [PowerPC] Implement writeNopDataUlrich Weigand2013-07-041-4/+8
| | | | | | | | | | | This implements a proper PPCAsmBackend::writeNopData routine that actually writes PowerPC nop instructions. This fixes the last remaining difference in object file output (text section) between the integrated assembler and GNU as that I've seen anywhere. llvm-svn: 185662
* Remove an unneeded call to 'UpdateThumbVFPPredicate', spotted by Amaury.Joey Gouly2013-07-041-1/+0
| | | | llvm-svn: 185651
* Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} ↵Joey Gouly2013-07-044-2/+94
| | | | | | | | | instructions. This adds a new decoder table/namespace 'VFPV8', as these instructions have their top 4 bits as 0b1111, while other Thumb instructions have 0b1110. llvm-svn: 185642
* [PowerPC] Add all trap mnemonicsUlrich Weigand2013-07-041-0/+31
| | | | | | | This adds support for all basic and extended variants of the trap instructions to the asm parser. llvm-svn: 185638
* [PowerPC] Add asm parser support for CR expressionsUlrich Weigand2013-07-042-5/+84
| | | | | | | | This adds support for specifying condition registers and condition register fields via expressions using the symbols defined by the PowerISA, like "4*cr2+eq". llvm-svn: 185633
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-047-29/+0
| | | | | | These exception-related opcodes are not used any longer. llvm-svn: 185625
* Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.Joey Gouly2013-07-042-1/+57
| | | | llvm-svn: 185620
* Add a space between closing template '>' to unbreak build.Craig Topper2013-07-041-3/+3
| | | | llvm-svn: 185607
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-047-15/+15
| | | | | | specifying the vector size. llvm-svn: 185606
* Revert r185595-185596 which broke buildbots.Jakob Stoklund Olesen2013-07-047-0/+29
| | | | | | | Revert "Simplify landing pad lowering." Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes." llvm-svn: 185600
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-037-29/+0
| | | | | | These exception-related opcodes are not used any longer. llvm-svn: 185596
* Have ARMBaseRegisterInfo::getCallPreservedMask return the 'correct' mask for ↵Stephen Lin2013-07-032-10/+13
| | | | | | | | the GHC calling convention. This is purely academic because GHC calls are always tail calls so the register mask will never be used; however, this change makes the code clearer and brings the ARM implementation of the GHC calling convention in line with the X86 implementation. Also, it might save someone else some time trying to figuring out what is happening... llvm-svn: 185592
* [ARM] Improve the instruction selection of vector loads.Quentin Colombet2013-07-031-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | In the ARM back-end, build_vector nodes are lowered to a target specific build_vector that uses floating point type. This works well, unless the inserted bitcasts survive until instruction selection. In that case, they incur moves between integer unit and floating point unit that may result in inefficient code. In other words, this conversion may introduce artificial dependencies when the code leading to the build vector cannot be completed with a floating point type. In particular, this happens when loads are not aligned. Before this patch, in that case, the compiler generates general purpose loads and creates the floating point vector from them, instead of directly using the vector unit. The patch uses a vector friendly sequence of code when the inserted bitcasts to floating point survived DAGCombine. This is done by a target specific DAGCombine that changes the target specific build_vector into a sequence of insert_vector_elt that get rid of the bitcasts. <rdar://problem/14170854> llvm-svn: 185587
* [PowerPC] FreeBSD does not require f128 in its data layout string.Bill Schmidt2013-07-031-1/+1
| | | | | | Long double is 64 bits on FreeBSD PPC, so the f128 entry is superfluous. llvm-svn: 185583
* ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying ↵Tilmann Scheller2013-07-031-9/+5
| | | | | | | | | | | | | | certain Thumb2 add immediate T3 encodings. Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding. The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process. This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly. Fixes <rdar://problem/14224440>. llvm-svn: 185575
* [PowerPC] Support lmw/stmw in the asm parserUlrich Weigand2013-07-031-0/+8
| | | | | | | This adds support for the load/store multiple instructions, currently used by the asm parser only. llvm-svn: 185564
* [PowerPC] Use mtocrf when availableUlrich Weigand2013-07-037-11/+38
| | | | | | | | | | | | | | | | | | | | Just as with mfocrf, it is also preferable to use mtocrf instead of mtcrf when only a single CR register is to be written. Current code however always emits mtcrf. This probably does not matter when using an external assembler, since the GNU assembler will in fact automatically replace mtcrf with mtocrf when possible. It does create inefficient code with the integrated assembler, however. To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and uses those instead of MTCRF/MTCRF8 everything. Just as done in the MFOCRF patch committed as 185556, these patterns will be converted back to MTCRF if MTOCRF is not available on the machine. As a side effect, this allows to modify the MTCRF pattern to accept the full range of mask operands for the benefit of the asm parser. llvm-svn: 185561
* [PowerPC] Always use mfocrf if availableUlrich Weigand2013-07-039-65/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When accessing just a single CR register, it is always preferable to use mfocrf instead of mfcr, if the former is available on the CPU. Current code makes that distinction in many, but not all places where a single CR register value is retrieved. One missing location is PPCRegisterInfo::lowerCRSpilling. To fix this and make this simpler in the future, this patch changes the bulk of the back-end to always assume mfocrf is available and simply generate it when needed. On machines that actually do not support mfocrf, the instruction is replaced by mfcr at the very end, in EmitInstruction. This has the additional benefit that we no longer need the MFCRpseud hack, since before EmitInstruction we always have a MFOCRF instruction pattern, which already models data flow as required. The patch also adds the MFOCRF8 version of the instruction, which was missing so far. Except for the PPCRegisterInfo::lowerCRSpilling case, no change in generated code intended. llvm-svn: 185556
* [PowerPC] Remove dead code from PPCDAGToDAGISel::SelectSETCCUlrich Weigand2013-07-031-23/+5
| | | | | | | | | | | | | | | | The subroutine getCRIdxForSetCC has a parameter "Other" and comment: If this returns with Other != -1, then the returned comparison is an or of two simpler comparisons. However for at least the last five years this routine has never returned a value of Other != -1; these cases are now handled differently to begin with. This patch removes the parameter and the code in SelectSETCC that attempted to handle the Other != -1 case. llvm-svn: 185541
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-035-19/+19
| | | | | | specifying the vector size. llvm-svn: 185540
* [PowerPC] Make specialized AltiVec patterns isCodeGenOnlyUlrich Weigand2013-07-031-2/+3
| | | | | | | | | | | A couple of AltiVec patterns are just specialized forms of the generic instruction pattern, and should therefore be marked isCodeGenOnly to avoid confusing the asm parser: VCFSX_0, VCTUXS_0, VCFUX_0, VCTSXS_0, and V_SETALLONES. Noticed by inspection of the generated PPCGenAsmMatcher.inc. llvm-svn: 185533
* [PowerPC] Support mtspr/mfspr in the asm parserUlrich Weigand2013-07-032-11/+20
| | | | | | | | | This adds support for the generic forms of mtspr/mfspr for the asm parser. The compiler will continue to use the specialized patters for mtlr etc. since those are needed to correctly describe data flow. llvm-svn: 185532
* [SystemZ] Fold more spillsRichard Sandiford2013-07-035-251/+369
| | | | | | | | | | | | | | | Add a mapping from register-based <INSN>R instructions to the corresponding memory-based <INSN>. Use it to cut down on the number of spill loads. Some instructions extend their operands from smaller fields, so this required a new TSFlags field to say how big the unextended operand is. This optimisation doesn't trigger for C(G)R and CL(G)R because in practice we always combine those instructions with a branch. Adding a test for every other case probably seems excessive, but it did catch a missed optimisation for DSGF (fixed in r185435). llvm-svn: 185529
* This corrects the implementation of Thumb ADR instruction. There are three ↵Mihai Popa2013-07-036-8/+46
| | | | | | | | | | issues: 1. it should accept only 4-byte aligned addresses 2. the maximum offset should be 1020 3. it should be encoded with the offset scaled by two bits llvm-svn: 185528
* ARM: relax the atomic release barrier to "dmb ishst" on SwiftTim Northover2013-07-031-1/+11
| | | | | | | | | | | Swift cores implement store barriers that are stronger than the ARM specification but weaker than general barriers. They are, in fact, just about enough to provide the ordering needed for atomic operations with release semantics. This patch makes use of that quirk. llvm-svn: 185527
* [SystemZ] Rename mapping table fieldsRichard Sandiford2013-07-032-37/+37
| | | | | | | | | | | | | Rename Function->DispKey and PairType->DispSize. I'd originally used "Function" because I thought it might be useful for other InstMappings. However, it turns out that having two very similar instructions with the same Function makes it pretty useless for anything other than the displacement size key. Other InstMappings will want the key to be defined for only one instruction in the pair. No behavioural change intended. llvm-svn: 185526
* [SystemZ] Fix caller-allocated save slot FIXMERichard Sandiford2013-07-033-46/+21
| | | | | | | Get rid of some old code (and associated FIXME) for handling the caller-allocated register save area. No behavioural change intended. llvm-svn: 185525
* [XCore] Whitespace fixes, no functionality change.Richard Osborne2013-07-031-3/+3
| | | | llvm-svn: 185519
* [XCore] Add ISel pattern for LDWCPRichard Osborne2013-07-031-8/+7
| | | | | | Patch by Robert Lytton. llvm-svn: 185518
* Added posix function gettimeofday to LibFunc::Func for all platforms but ↵Michael Gottesman2013-07-031-0/+2
| | | | | | | | | | | Windows. *NOTE* In a recent version of posix, they added the restrict keyword to the arguments for this function. From some spelunking it seems that on some platforms, the call has restrict on its arguments and others it does not. Thus I left off the restrict keyword from the function prototype in the comment. llvm-svn: 185501
* SystemZInstrInfo.cpp: Tweak an assertion. [-Wunused-variable]NAKAMURA Takumi2013-07-031-2/+2
| | | | llvm-svn: 185499
* [PowerPC] PR16512 - Support TLS call sequences in the asm parserUlrich Weigand2013-07-022-2/+26
| | | | | | | | | This patch now adds support for recognizing TLS call sequences in the asm parser. This needs a new pattern BL8_TLS, which is like BL8_NOP_TLS except without nop. That pattern is used for the asm parser only. llvm-svn: 185478
* [PowerPC] Rework TLS call operand processingUlrich Weigand2013-07-026-23/+40
| | | | | | | | | | | | | | | | | | | | | | | | | As part of the global-dynamic and local-dynamic TLS sequences, we need to use a special form of the call instruction: bl __tls_get_addr(sym@tlsld) bl __tls_get_addr(sym@tlsgd) which generates two fixups. The current implementation of this causes problems with recognizing this form in the asm parser. To fix this, this patch reworks operand processing for this special form by using a single operand to hold both __tls_get_addr and sym@tlsld and defining a print method to output the above form, and an encoding method to generate the two fixups. As a side simplification, the patch replaces the two instruction patterns BL8_NOP_TLSGD and BL8_NOP_TLSLD by a single BL8_NOP_TLS, since the patterns already operate in an identical fashion (whether we have a local-dynamic or global-dynamic symbol is already encoded in the symbol modifier). No change in code generation intended. llvm-svn: 185477
* [PowerPC] Remove VK_PPC_TLSGD and VK_PPC_TLSLDUlrich Weigand2013-07-022-6/+4
| | | | | | | | | | | | | | | The PowerPC-specific modifiers VK_PPC_TLSGD and VK_PPC_TLSLD correspond exactly to the generic modifiers VK_TLSGD and VK_TLSLD. This causes some confusion with the asm parser, since VK_PPC_TLSGD is output as @tlsgd, which is then read back in as VK_TLSGD. To avoid this confusion, this patch removes the PowerPC-specific modifiers and uses the generic modifiers throughout. (The only drawback is that the generic modifiers are printed in upper case while the usual convention on PowerPC is to use lower-case modifiers. But this is just a cosmetic issue.) llvm-svn: 185476
* SystemZ: Fold variable into assertion.Benjamin Kramer2013-07-021-2/+2
| | | | llvm-svn: 185475
* [PowerPC] Support TLS variables in debug infoUlrich Weigand2013-07-022-0/+13
| | | | | | | | | This adds an implementation of getDebugThreadLocalSymbol for (64-bit) PowerPC. This needs to return a generic MCExpr since on ppc64, we need to add a bias of 0x8000 to the value returned by the R_PPC64_DTPREL64 relocation. llvm-svn: 185461
* [DebugInfo] Allow getDebugThreadLocalSymbol to return MCExprUlrich Weigand2013-07-023-3/+3
| | | | | | | | | | | This allows getDebugThreadLocalSymbol to return a generic MCExpr instead of just a MCSymbolRefExpr. This is in preparation for supporting debug info for TLS variables on PowerPC, where we need to describe the variable location using a more complex expression than just MCSymbolRefExpr. llvm-svn: 185460
* Hexagon: Avoid unused variable warnings in Release builds.Benjamin Kramer2013-07-021-6/+2
| | | | llvm-svn: 185445
* Remove address spaces from MC.Rafael Espindola2013-07-028-26/+18
| | | | | | | | This is dead code since PIC16 was removed in 2010. The result was an odd mix, where some parts would carefully pass it along and others would assert it was zero (most of the object streamer for example). llvm-svn: 185436
* [SystemZ] Use DSGFR over DSGR in more casesRichard Sandiford2013-07-024-6/+12
| | | | | | | | | | Fixes some cases where we were using full 64-bit division for (sdiv i32, i32) and (sdiv i64, i32). The "32" in "SDIVREM32" just refers to the second operand. The first operand of all *DIVREM*s is a GR128. llvm-svn: 185435
* [SystemZ] Use MVC to spill loads and storesRichard Sandiford2013-07-023-13/+113
| | | | | | | | | | | | | | | | | | | | | Try to use MVC when spilling the destination of a simple load or the source of a simple store. As explained in the comment, this doesn't yet handle the case where the load or store location is also a frame index, since that could lead to two simultaneous scavenger spills, something the backend can't handle yet. spill-02.py tests that this restriction kicks in, but unfortunately I've not yet found a case that would fail without it. The volatile trick I used for other scavenger tests doesn't work here because we can't use MVC for volatile accesses anyway. I'm planning on relaxing the restriction later, hopefully with a test that does trigger the problem... Tests @f8 and @f9 also showed that L(G)RL and ST(G)RL were wrongly classified as SimpleBDX{Load,Store}. It wouldn't be easy to test for that bug separately, which is why I didn't split out the fix as a separate patch. llvm-svn: 185434
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