summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* [Sparc] This provides support for itineraries on Sparc.Chris Dewhurst2016-04-225-159/+417
| | | | | | | | | | | | Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future. The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this. As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary. Phabricator Review: http://reviews.llvm.org/D19359 llvm-svn: 267121
* The following code would not work before this patch, due to the inability to ↵Chris Dewhurst2016-04-221-1/+1
| | | | | | | | | | | | | | | | | | | | | take the address of a global object: void func1() { ... } int main(int argc, char** argv) { void (*pFunc)(); pFunc = &func1 pFunc(); ... } Phabricator review: http://reviews.llvm.org/D19368 llvm-svn: 267120
* [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructionsZlatko Buljan2016-04-223-1/+60
| | | | | | Differential Revision: http://reviews.llvm.org/D18687 llvm-svn: 267114
* Fix some spelling mistakesDavid Majnemer2016-04-221-2/+2
| | | | llvm-svn: 267112
* [SystemZ] Mark CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF as Expand instead of Custom ↵Craig Topper2016-04-221-8/+2
| | | | | | since the custom logic just did what Expand does when CTTZ/CTLZ are Legal. NFC llvm-svn: 267109
* [Lanai] Set CTLZ_ZERO_UNDEF/CTTZ_ZERO_UNDEF to Expand instead of Legal so ↵Craig Topper2016-04-222-11/+2
| | | | | | they will be converted to CTLZ/CTTZ by LegalizeDAG. Remove extra instructions that only existed to to contain patterns that match the zero_undef operations. NFC llvm-svn: 267108
* [Lanai] Remove unused methods declarations. NFCCraig Topper2016-04-221-3/+0
| | | | llvm-svn: 267107
* AMDGPU/SI: add llvm.amdgcn.ps.live intrinsicNicolai Haehnle2016-04-224-16/+55
| | | | | | | | | | | | | | | | | | | | | | | Summary: This intrinsic returns true if the current thread belongs to a live pixel and false if it belongs to a pixel that we are executing only for derivative computation. It will be used by Mesa to implement gl_HelperInvocation. Note that for pixels that are killed during the shader, this implementation also returns true, but it doesn't matter because those pixels are always disabled in the EXEC mask. This unearthed a corner case in the instruction verifier, which complained about a v_cndmask 0, 1, exec, exec<imp-use> instruction. That's stupid but correct code, so make the verifier accept it as such. Reviewers: arsenm, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19191 llvm-svn: 267102
* [AVX512] Teach lowering to use vplzcntd/q to implement 128/256-bit ↵Craig Topper2016-04-221-9/+6
| | | | | | CTTZ_ZERO_UNDEF even without VLX support. We can just extend to 512-bits and extract like we do for CTLZ. llvm-svn: 267100
* [MachineCombiner] Support for floating-point FMA on ARM64Gerolf Hoflehner2016-04-224-35/+557
| | | | | | | | | | | | | | | | Evaluates fmul+fadd -> fmadd combines and similar code sequences in the machine combiner. It adds support for float and double similar to the existing integer implementation. The key features are: - DAGCombiner checks whether it should combine greedily or let the machine combiner do the evaluation. This is only supported on ARM64. - It gives preference to throughput over latency: the heuristic used is to combine always in loops. The targets decides whether the machine combiner should optimize for throughput or latency. - Supports for fmadd, f(n)msub, fmla, fmls patterns - On by default at O3 ffast-math llvm-svn: 267098
* [WebAssembly] Limit alignment hints to natural alignment.Dan Gohman2016-04-211-3/+9
| | | | | | This follows the current binary format rules. llvm-svn: 267082
* ARM: restrict register class for WIN__DBZCHKSaleem Abdulrasool2016-04-211-2/+2
| | | | | | | | | | | WIN__DBZCHK will insert a CBZ instruction into the stream. This instruction reserves 3 bits for the condition register (rn). As such, we must ensure that we restrict the register to a low register. Use the tGPR class instead of GPR to ensure that this is properly constrained. In debug builds, we would attempt to use lr as a condition register which would silently get truncated with no hint that the register selection was incorrect. llvm-svn: 267080
* MachO: enable .data_region directives everywhereTim Northover2016-04-211-1/+0
| | | | | | | | | | We'd disabled them on x86 because back in the early days some host tools couldn't handle the new load commands. This no longer holds: anyone capable of deploying Clang should be able to deploy its copies of ar/ranlib/etc. rdar://25254790 llvm-svn: 267075
* [Hexagon] Properly recognize register alt namesKrzysztof Parzyszek2016-04-213-38/+47
| | | | llvm-svn: 267038
* [Hexagon] Expand handling of the small-data/bss sectionKrzysztof Parzyszek2016-04-214-67/+367
| | | | llvm-svn: 267034
* [RegisterBankInfo] Change the API for the verify methods.Quentin Colombet2016-04-211-1/+1
| | | | | | | Return bool instead of void so that it is natural to put the calls into asserts. llvm-svn: 267033
* AMDGPU: Fix debug name of pass to better matchMatt Arsenault2016-04-211-1/+1
| | | | | | I get this wrong every time I try to debug this. llvm-svn: 267030
* Split IntrReadArgMem into IntrReadMem and IntrArgMemOnlyNicolai Haehnle2016-04-211-1/+1
| | | | | | | | | | | | | | | | | | Summary: IntrReadWriteArgMem simply becomes IntrArgMemOnly. So there are fewer intrinsic properties that express their orthogonality better, and correspond more closely to the corresponding IR attributes. Suggested by: Philip Reames Reviewers: joker.eph, reames, tstellarAMD Subscribers: jholewinski, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19291 llvm-svn: 267021
* [PowerPC] [SSP] Fix stack guard load for 32-bit.Marcin Koscielnicki2016-04-211-1/+1
| | | | | | | | r266809 incorrectly used LD to load the stack guard, it should be LWZ. Differential Revision: http://reviews.llvm.org/D19358 llvm-svn: 267017
* [mips][microMIPS] Implement ldpc instructionZoran Jovanovic2016-04-213-1/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D15009 llvm-svn: 266990
* [mips][microMIPS] Add R_MICROMIPS_PC19_S2 relocationZoran Jovanovic2016-04-214-2/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D14915 llvm-svn: 266988
* [mips][microMIPS] Add R_MICROMIPS_PC26_S1 relocationZoran Jovanovic2016-04-214-1/+24
| | | | | | Differential Revision: http://reviews.llvm.org/D14822 llvm-svn: 266985
* [AMDGPU] Assembler: prevent parseDPPCtrlOps from eating invalid tokensSam Kolton2016-04-211-2/+14
| | | | | | | | | | Reviewers: nhaustov, tstellarAMD Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D19317 llvm-svn: 266984
* [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructionsZlatko Buljan2016-04-211-5/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D18855 llvm-svn: 266980
* [mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL ↵Zlatko Buljan2016-04-214-12/+25
| | | | | | | | instructions and add tests for LWM32 and SWM32 Differential Revision: http://reviews.llvm.org/D19150 llvm-svn: 266977
* [AArch64][CodeGen] Fix of PR27158: incorrect peephole optimization in ↵Evgeny Astigeevich2016-04-212-75/+157
| | | | | | | | | | | | | | | | AArch64InstrInfo::optimizeCompareInstr AArch64InstrInfo::optimizeCompareInstr has bug PR27158 which causes generation of incorrect code. A compare instruction is substituted with another instruction which does not produce the same flags as the original compare instruction. This patch contains: 1. Fix of the bug. 2. A regression test in MIR. 3. A new test to check that SUBS is replaced by SUB. Differential Revision: http://reviews.llvm.org/D18838 llvm-svn: 266969
* [AVX512] Add CTTZ support for v8i64 and v16i32 vectors.Craig Topper2016-04-211-0/+1
| | | | llvm-svn: 266968
* [AVX512] Add support for lowering CTTZ v64i8 and v32i16 with BWI instructions.Craig Topper2016-04-211-0/+1
| | | | llvm-svn: 266963
* [X86] Remove redundant calls to setOperationAction for ↵Craig Topper2016-04-211-19/+2
| | | | | | EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT from SSE41 block. They were already done in an earlier block. NFC llvm-svn: 266962
* [X86] Remove some operations from the default Expand all vector ops loop. ↵Craig Topper2016-04-211-22/+26
| | | | | | Instead let them stay Legal and mark them Expand for specific types where needed. Reduces overall number of calls to setOperationAction. NFC llvm-svn: 266961
* [X86] Remove old leftover MMX code that sets various 64-bit vector ↵Craig Topper2016-04-211-17/+0
| | | | | | operations to Expand. These vector types aren't legal so these operations would never make it far enough to need to expand. NFC llvm-svn: 266960
* [X86] Remove unnecessary setting of CTTZ_ZERO_UNDEF to Custom for vector ↵Craig Topper2016-04-211-5/+0
| | | | | | | | types where we can't do any better than the Custom lowering of CTTZ. LegalizeVectorOps will expand to CTTZ since its marked Custom. CTTZ_ZERO_UNDEF can be custom lowered specially if CTLZ is supported. Otherwise CTTZ and CTTZ_ZERO_UNDEF are handled the same way by using CTPOP and bitmath. llvm-svn: 266952
* [AVX512] Add support for popcount of v8i64 and v16i32 with and without BWI ↵Craig Topper2016-04-211-0/+13
| | | | | | | | instructions. Without BWI we have to split the vectors into 256-bit vectors so we can use AVX2 pshufb and then concatenate the results. llvm-svn: 266950
* [Hexagon] Add -mv.. options to override CPU selectionKrzysztof Parzyszek2016-04-201-3/+39
| | | | | | | This is for compatibility with scripts that use -mv5, etc. with the assembler. llvm-svn: 266918
* [MC] Silence warning due to unused variable in !Debug builds.Davide Italiano2016-04-201-0/+1
| | | | llvm-svn: 266901
* [lanai] Add subword scheduling itineraries.Jacques Pienaar2016-04-202-17/+34
| | | | | | | | Differentiate between word and subword memory operations as they take different amount of cycles to complete. This just adds a basic model of the subword latency to the scheduler. llvm-svn: 266898
* [MC] EmitNop: Make an assertion more useful.Davide Italiano2016-04-201-1/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D19334 llvm-svn: 266895
* [Hexagon] Fix handling of lcomm directiveKrzysztof Parzyszek2016-04-201-7/+12
| | | | | | Patch by Colin LeMahieu. llvm-svn: 266882
* [RDF] Consider register as live if any alias is liveKrzysztof Parzyszek2016-04-201-2/+2
| | | | | | This only affects the recomputation of kill flags. llvm-svn: 266875
* [mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructionsZoran Jovanovic2016-04-204-24/+195
| | | | | | Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
* AMDGPU/SI: Assembler: improvements to support trap handlers.Nikolay Haustov2016-04-202-70/+124
| | | | | | | | | | | | Add ParseAMDGPURegister which can be invoked recursively for parsing lists. Rename getRegForName to getSpecialRegForName. Support legacy SP3 register list syntax: [s2,s3,s4,s5] or [flat_scratch_lo,flat_scratch_hi]. Add 64-bit registers TBA, TMA where missing. Add some tests. Differential Revision: http://reviews.llvm.org/D19163 llvm-svn: 266865
* [X86] enable PIE for functionsAsaf Badouh2016-04-204-44/+40
| | | | | | | | Call locally defined function directly for PIE/fPIE Differential Revision: http://reviews.llvm.org/D19226 llvm-svn: 266863
* [mips][microMIPS]Implement CFC*, CTC* and LDC* instructionsHrvoje Varga2016-04-2010-8/+172
| | | | | | Differential Revision: http://reviews.llvm.org/D18640 llvm-svn: 266861
* [AVX512] Add popcount support for v32i16 and v64i8.Craig Topper2016-04-201-3/+3
| | | | llvm-svn: 266858
* [X86] Mark some floating point operations that are always expanded for ↵Craig Topper2016-04-201-13/+17
| | | | | | vector types as Expand in a floating point only loop instead of looping through all vector types. llvm-svn: 266850
* [X86] Don't mark vector loads and shifts Expand in advance. Loads are always ↵Craig Topper2016-04-201-23/+4
| | | | | | marked Legal or Promote for all the legal types later. Shifts are always marked custom. NFC llvm-svn: 266849
* [X86] Merge the two different SSE2 blocks in the X86TargetLowering ↵Craig Topper2016-04-201-21/+19
| | | | | | constructor. Also qualfiy the XOP block with !useSoftFloat to match the other vector blocks. llvm-svn: 266848
* [X86] Don't set vector FADD,FSUB,FMUL,FDIV,FNEG,FSQRT to Expand early. For ↵Craig Topper2016-04-201-27/+0
| | | | | | every legal FP type we either set them to Legal or Custom anyway. So let them stay defaulted to Legal and only change when they need to be Custom. llvm-svn: 266847
* [SystemZ] Add support for llvm.thread.pointer intrinsic.Marcin Koscielnicki2016-04-202-8/+19
| | | | | | Differential Revision: http://reviews.llvm.org/D19054 llvm-svn: 266844
* MipsAsmParser::loadImmediate(): Prune an obsolete \param in r266602. ↵NAKAMURA Takumi2016-04-201-1/+0
| | | | | | [-Wdocumentation] llvm-svn: 266841
OpenPOWER on IntegriCloud