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* Fix PR9127 by reversing the operands even if they have more then one use.Rafael Espindola2011-02-031-2/+2
| | | | | | | | Reversing the operands allows us to fold, but doesn't force us to. Also, at this point the DAG is still being optimized, so the check for hasOneUse is not very precise. llvm-svn: 124773
* Update comment to match my recent change.Bob Wilson2011-02-021-2/+2
| | | | llvm-svn: 124725
* SimplifyCFG: Turn switches into sub+icmp+branch if possible.Benjamin Kramer2011-02-021-48/+0
| | | | | | | | | | | | | | | | | This makes the job of the later optzn passes easier, allowing the vast amount of icmp transforms to chew on it. We transform 840 switches in gcc.c, leading to a 16k byte shrink of the resulting binary on i386-linux. The testcase from README.txt now compiles into decl %edi cmpl $3, %edi sbbl %eax, %eax andl $1, %eax ret llvm-svn: 124724
* Add support for trampolines on the XCore.Richard Osborne2011-02-024-1/+72
| | | | llvm-svn: 124722
* Fixed a bug in the disassembler where the mandatory 0x66Sean Callanan2011-02-021-0/+1
| | | | | | | | prefix would be misinterpreted in some cases on 32-bit x86 platforms. Thanks to Olivier Meurant for identifying the bug. llvm-svn: 124709
* Given a pair of floating point load and store, if there are no other uses ofEvan Cheng2011-02-022-2/+9
| | | | | | | | | | | | | | | | | | | the load, then it may be legal to transform the load and store to integer load and store of the same width. This is done if the target specified the transformation as profitable. e.g. On arm, this can transform: vldr.32 s0, [] vstr.32 s0, [] to ldr r12, [] str r12, [] rdar://8944252 llvm-svn: 124708
* PR9081: Split up LDM instruction with deprecated use of both LR and PC.Bob Wilson2011-02-011-2/+3
| | | | | | | This is completely untested but pretty straightforward, so hopefully I got it right. llvm-svn: 124694
* Fix imm printing for logical instructions.Anton Korobeynikov2011-02-013-24/+45
| | | | | | Patch by Brian G. Lucas! llvm-svn: 124679
* Test commit - fix a double 'should' in a comment.Carl Norum2011-02-011-1/+1
| | | | llvm-svn: 124652
* Patches to build EFI with Clang/LLVM. By Carl Norum.Evan Cheng2011-02-016-16/+36
| | | | llvm-svn: 124639
* Keep track of incoming argument's location while emitting LiveIns.Devang Patel2011-01-316-25/+25
| | | | llvm-svn: 124611
* Fix vector sign extend to put the source and destination types in theDavid Greene2011-01-311-3/+3
| | | | | | correct places. llvm-svn: 124601
* add a note, progress unblocked by PR8575 being fixed.Chris Lattner2011-01-311-0/+48
| | | | llvm-svn: 124599
* Save a mapping between original and cloned constpool entries.Anton Korobeynikov2011-01-302-0/+25
| | | | llvm-svn: 124570
* Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, ↵Benjamin Kramer2011-01-301-21/+0
| | | | | | | | | | | | | | | | | | c1+c2) when c1 equals the amount of bits that are truncated off. This happens all the time when a smul is promoted to a larger type. On x86-64 we now compile "int test(int x) { return x/10; }" into movslq %edi, %rax imulq $1717986919, %rax, %rax movq %rax, %rcx shrq $63, %rcx sarq $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax" addl %ecx, %eax This fires 96 times in gcc.c on x86-64. llvm-svn: 124559
* PR9030: Fix disassembly of ARM "mov pc, lr" instruction.Bob Wilson2011-01-281-2/+2
| | | | | | Patch by Jyun-Yan You. llvm-svn: 124492
* Fix PLD encoding.Evan Cheng2011-01-271-2/+2
| | | | llvm-svn: 124458
* Changed llvm-mc arm target to give an error if .syntax divided is used. SinceKevin Enderby2011-01-271-1/+1
| | | | | | only .syntax unified is supported. llvm-svn: 124454
* [AVX] Clean up the code to configure target lowering for AVX. SpecifyDavid Greene2011-01-271-73/+47
| | | | | | | how to lower more/new operations. This is a prerequisite for adding additional AVX lowering. llvm-svn: 124447
* Introduce virtual ParseRegister method in TargetAsmParser.Roman Divacky2011-01-273-6/+19
| | | | | | Create override of this method in X86/ARM/MBlaze. llvm-svn: 124378
* Use the incoming VT not the VT of where we're trying to store to determineEric Christopher2011-01-271-2/+2
| | | | | | | | if we can store a value. Also, the exclusion is or, not and. Fixes rdar://8920247. llvm-svn: 124357
* lib/Target/X86/X86ISelDAGToDAG.cpp: __main should be WINCALL64 on Win64.NAKAMURA Takumi2011-01-271-1/+1
| | | | | | CALL64 marks %xmm* as dead. llvm-svn: 124354
* Add support for printing out floating point values from the ARM assemblyBill Wendling2011-01-261-2/+27
| | | | | | | parser. The parser will always give us a binary representation of the floating point number. llvm-svn: 124318
* [AVX] Add INSERT_SUBVECTOR and support it on x86. This provides aDavid Greene2011-01-262-1/+23
| | | | | | | | default implementation for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VINSERTF128 if AVX is available. llvm-svn: 124307
* [AVX] Support EXTRACT_SUBVECTOR on x86. This provides a defaultDavid Greene2011-01-262-0/+13
| | | | | | | | implementation of EXTRACT_SUBVECTOR for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VEXTRACTF128 if AVX is available. llvm-svn: 124292
* fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructionsBruno Cardoso Lopes2011-01-261-0/+1
| | | | llvm-svn: 124288
* Add needed braces.Bill Wendling2011-01-261-1/+2
| | | | llvm-svn: 124273
* Target/X86: Tweak win64's tailcall.NAKAMURA Takumi2011-01-267-12/+49
| | | | llvm-svn: 124272
* Fix whitespace.NAKAMURA Takumi2011-01-266-132/+129
| | | | llvm-svn: 124270
* lib/Target/X86/X86RegisterInfo.cpp: Fix whitespace.NAKAMURA Takumi2011-01-261-3/+3
| | | | llvm-svn: 124268
* lib/Target/X86/X86RegisterInfo.cpp: Fix a typo in comment.NAKAMURA Takumi2011-01-261-1/+1
| | | | llvm-svn: 124267
* Revert 124230. It was causing test failures.Bill Wendling2011-01-251-4/+2
| | | | llvm-svn: 124233
* The floating point value is encoded in its binary form as an Imm. Convert itBill Wendling2011-01-251-2/+4
| | | | | | appropriately so that it prints out the decimal representation. llvm-svn: 124230
* Don't merge restore with tail call instruction.Evan Cheng2011-01-251-1/+6
| | | | llvm-svn: 124167
* Provide correct registers for EH stuff on ARMAnton Korobeynikov2011-01-241-3/+4
| | | | llvm-svn: 124151
* fix a missing shuffle pattern, PR9009. Patch by Artiom Myaskouvskey!Chris Lattner2011-01-241-0/+3
| | | | llvm-svn: 124102
* this isn't a memset, we do convert dest[i] to one though :)Chris Lattner2011-01-241-8/+0
| | | | llvm-svn: 124097
* with recent work, we now optimize this into:Chris Lattner2011-01-241-20/+0
| | | | | | | | | | | define i32 @foo(i32 %x) nounwind readnone ssp { entry: %tobool = icmp eq i32 %x, 0 %tmp5 = select i1 %tobool, i32 2, i32 1 ret i32 %tmp5 } llvm-svn: 124091
* Add a memset loop that LoopIdiomRecognize doesn't recognize.Anders Carlsson2011-01-231-0/+8
| | | | llvm-svn: 124082
* Initialize MCNoExecStack.Rafael Espindola2011-01-231-0/+1
| | | | llvm-svn: 124079
* Add support for the --noexecstack option.Rafael Espindola2011-01-234-7/+12
| | | | llvm-svn: 124077
* Null initialize a few variables flagged byTed Kremenek2011-01-233-3/+3
| | | | | | | | | | clang's -Wuninitialized-experimental warning. While these don't look like real bugs, clang's -Wuninitialized-experimental analysis is stricter than GCC's, and these fixes have the benefit of being general nice cleanups. llvm-svn: 124073
* Delay the creation of eh_frame so that the user can change the defaults.Rafael Espindola2011-01-231-1/+0
| | | | | | Add support for SHT_X86_64_UNWIND. llvm-svn: 124059
* Remove more duplicated code.Rafael Espindola2011-01-235-21/+21
| | | | llvm-svn: 124056
* Remove duplicated code.Rafael Espindola2011-01-236-15/+21
| | | | llvm-svn: 124054
* Pass sret arguments through the stack instead of through registers in Sparc ↵Venkatraman Govindaraju2011-01-223-4/+75
| | | | | | backend. It makes the code generated more compliant with the sparc32 ABI. llvm-svn: 124030
* Added ICC, FCC as uses of movcc instruction to generate correct code when ↵Venkatraman Govindaraju2011-01-221-42/+51
| | | | | | -mattr=v9 is used. llvm-svn: 124027
* Sparc backend: Venkatraman Govindaraju2011-01-213-23/+28
| | | | | | | Rename FLUSH to FLUSHW. Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used. llvm-svn: 123997
* Last round of fixes for movw + movt global address codegen.Evan Cheng2011-01-219-75/+136
| | | | | | | | | | 1. Fixed ARM pc adjustment. 2. Fixed dynamic-no-pic codegen 3. CSE of pc-relative load of global addresses. It's now enabled by default for Darwin. llvm-svn: 123991
* Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm",Bruno Cardoso Lopes2011-01-212-15/+24
| | | | | | | qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This is described in ARM manuals and matches the encoding used by the gnu assembler. llvm-svn: 123975
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