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* Fix whitespace indentation. NFCI.Simon Pilgrim2017-07-131-2/+2
| | | | llvm-svn: 307894
* [ARM] GlobalISel: Move local variable. NFCDiana Picus2017-07-131-4/+10
| | | | | | | Move a local variable from outside a switch to inside every case that needs it (which isn't all of the cases, of course). llvm-svn: 307893
* [AVR] Fix broken indentationDylan McKay2017-07-131-1/+1
| | | | llvm-svn: 307891
* [AVR] Add a 'LLVM_FALLTHROUGH' statement to the AsmParserDylan McKay2017-07-131-0/+1
| | | | | | Should fix warnings in the build. llvm-svn: 307890
* [ARM] Inline callee if its target-features are a subset of the callerFlorian Hahn2017-07-132-0/+54
| | | | | | | | | | | | | | | | | | | Summary: Similar to X86, it should be safe to inline callees if their target-features are a subset of the caller. As some subtarget features provide different instructions depending on whether they are set or unset (e.g. ThumbMode and ModeSoftFloat), we use a whitelist of target-features describing hardware capabilities only. Reviewers: kristof.beyls, rengolin, t.p.northover, SjoerdMeijer, peter.smith, silviu.baranga, efriedma Reviewed By: SjoerdMeijer, efriedma Subscribers: dschuff, efriedma, aemerson, sdardis, javed.absar, arichardson, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D34697 llvm-svn: 307889
* [AVR] Fix indirect calls to function pointersDylan McKay2017-07-131-2/+14
| | | | | | Patch by Carl Peto. llvm-svn: 307888
* fix typos in comments and error messges; NFCHiroshi Inoue2017-07-132-3/+3
| | | | llvm-svn: 307885
* [MIR] Add support for printing and parsing target MMO flagsGeoff Berry2017-07-132-0/+9
| | | | | | | | | | | | | | | | | Summary: Add target hooks for printing and parsing target MMO flags. Targets may override getSerializableMachineMemOperandTargetFlags() to return a mapping from string to flag value for target MMO values that should be serialized/parsed in MIR output. Add implementation of this hook for AArch64 SuppressPair MMO flag. Reviewers: bogner, hfinkel, qcolombet, MatzeB Subscribers: mcrosier, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D34962 llvm-svn: 307877
* AMDGPU: Fix converting unanalyzable global loads to SMRDMatt Arsenault2017-07-121-4/+5
| | | | | | | Not all memory dependence queries succeed, so this needs to be conservative if it fails. llvm-svn: 307861
* Add element atomic memset intrinsicDaniel Neilson2017-07-121-0/+11
| | | | | | | | | | | | | | Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memset intrinsic. This intrinsic is essentially memset with the implementation requirement that all stores used for the assignment are done with unordered-atomic stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: jfb, dschuff, sbc100, jgravelle-google, aheejin, efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D34885 llvm-svn: 307854
* [AArch64] Only run macro fusion for CPUs with any fusion support.Florian Hahn2017-07-121-1/+3
| | | | | | | | | | | | Reviewers: evandro, t.p.northover, javed.absar Reviewed By: evandro Subscribers: aemerson, rengolin, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34959 llvm-svn: 307851
* [AMDGPU] fcanonicalize elimination optimizationStanislav Mekhanoshin2017-07-121-9/+86
| | | | | | | | | | | | We are using multiplication by 1.0 to flush denormals and quiet sNaNs. That is possible to omit this multiplication if source of the fcanonicalize instruction is known to be flushed/quieted, i.e. if it comes from another instruction known to do the normalization and we are using IEEE mode to quiet sNaNs. Differential Revision: https://reviews.llvm.org/D35218 llvm-svn: 307848
* [AArch64] Add AArch64Subtarget::isFusion function.Florian Hahn2017-07-122-1/+8
| | | | | | | | | | | | | | | | | | | | | | Summary: isFusion returns true if the subtarget supports any kind of instruction fusion, similar to ARMSubtarget::isFusion. This was suggested in D34142. This changes the current behavior slightly, because the macro fusion mutation is now added to the PostRA MachineScheduler in case the subtarget supports any kind of fusion. I think that makes sense because if the PostRA MachineScheduler is run, there is potential that instructions scheduled back to back are re-scheduled. Reviewers: evandro, t.p.northover, joelkevinjones, joel_k_jones, steleman Reviewed By: joelkevinjones Subscribers: joel_k_jones, aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34958 llvm-svn: 307842
* [WebAssembly] Mark element atomic memcpy/memmove intrinsics as unsupportedHeejin Ahn2017-07-121-11/+10
| | | | | | | | | | | | | | | | Summary: Element atomic intrinsicAtomic instructions are not yet supported in WebAssembly, so we mark them as unsupported for the moment. Reviewers: sunfish, dschuff, sbc100 Reviewed By: dschuff, sbc100 Subscribers: jfb, sbc100, jgravelle-google Differential Revision: https://reviews.llvm.org/D35322 llvm-svn: 307841
* Remove unneeded use of #undef DEBUG_TYPE. NFCSam Clegg2017-07-121-1/+0
| | | | | | | | | | | Where is is needed (at the end of headers that define it), be consistent about its use. Also fix a few header guards that I found in the process. Differential Revision: https://reviews.llvm.org/D34916 llvm-svn: 307840
* [mips][mt][6/7] Add support for mftr, mttr instructions.Simon Dardis2017-07-126-0/+372
| | | | | | | | | | | | | | | | | Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 307836
* Fix to web assembly lib call listDaniel Neilson2017-07-121-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Revision 307796 caused an internal build break in WebAssembly bots in the form of a crash. ex: Here's the crash dump from one of the failing tests: /usr/local/google/home/blaikie/dev/llvm/build/default/./bin/llc < /usr/local/google/home/blaikie/dev/llvm/src/test/CodeGen/WebAssembly/global.ll -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | /usr/local/google/home/blaikie/dev/llvm/build/default/./bin/FileCheck /usr/local/google/home/blaikie/dev/llvm/src/test/CodeGen/WebAssembly/global.ll -- Exit Code: 2 Command Output (stderr): -- Stack dump: 0. Program arguments: build/default/./bin/llc -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals 1. Running pass 'Function Pass Manager' on module '<stdin>'. 2. Running pass 'WebAssembly Assembly Printer' on function '@call_memcpy' FileCheck error: '-' is empty. FileCheck command line: build/default/./bin/FileCheck src/test/CodeGen/WebAssembly/global.ll The problem is in lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp. There’s an array declared: 545 static const char * Fix to web assembly lib call list Summary: Revision 307796 caused an internal build break in WebAssembly bots in the form of a crash. ex: Here's the crash dump from one of the failing tests: /usr/local/google/home/blaikie/dev/llvm/build/default/./bin/llc < /usr/local/google/home/blaikie/dev/llvm/src/test/CodeGen/WebAssembly/global.ll -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | /usr/local/google/home/blaikie/dev/llvm/build/default/./bin/FileCheck /usr/local/google/home/blaikie/dev/llvm/src/test/CodeGen/WebAssembly/global.ll -- Exit Code: 2 Command Output (stderr): -- Stack dump: 0. Program arguments: build/default/./bin/llc -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals 1. Running pass 'Function Pass Manager' on module '<stdin>'. 2. Running pass 'WebAssembly Assembly Printer' on function '@call_memcpy' FileCheck error: '-' is empty. FileCheck command line: build/default/./bin/FileCheck src/test/CodeGen/WebAssembly/global.ll The problem is in lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp. There’s an array declared: static const char * RuntimeLibcallNames[RTLIB::UNKNOWN_LIBCALL] = { That is defining a runtime lib call name for each entry in the enum RTLIB:Libcall from include/llvm/CodeGen/RuntimeLibcalls.h. Revision 307796 added entries to the enum, but didn’t add entries to the RuntimeLibcallNames array, which caused a crash when attempting to access past the end of the array. This patch fixes the issue by adding the element atomic memmove to the WebAssembly arrays. Reviewed by: reames llvm-svn: 307831
* [x86] improve SBB optimizations for SETB/SETA with subtractSanjay Patel2017-07-121-26/+33
| | | | | | | | | | | | | | This is another step towards removing a combine that turns sext into select of constants and preparing the backend for an IR future where select is the canonical form. Earlier commits in this area: https://reviews.llvm.org/rL306040 https://reviews.llvm.org/rL306072 https://reviews.llvm.org/rL307404 (https://reviews.llvm.org/D34652) https://reviews.llvm.org/rL307471 llvm-svn: 307821
* GlobalISel: Handle selection of G_IMPLICIT_DEF in AArch64Justin Bogner2017-07-121-0/+3
| | | | | | | | A generic variant of IMPLICIT_DEF was added in r306875, but this survives to selection and hits a `Cannot Select`. Add handling that converts the note to a regular IMPLICIT_DEF. llvm-svn: 307817
* [mips][mt][5/7] Add support for fork and yield instructions.Simon Dardis2017-07-124-2/+65
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35252 llvm-svn: 307808
* [X86/FastIsel] Fall-back to SelectionDAG when lowering soft-floats.Davide Italiano2017-07-121-0/+3
| | | | | | | | | | FastIsel can't handle them, so we would end up crashing during register class selection. Fixes PR26522. Differential Revision: https://reviews.llvm.org/D35272 llvm-svn: 307797
* [mips][mt][4/7] Add IAS support for dvpe, evpe instructions.Simon Dardis2017-07-124-5/+28
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35251 llvm-svn: 307793
* [ARM] Adjust ifcvt heuristic for the diamond ifcvt caseJohn Brawn2017-07-121-0/+3
| | | | | | | | | When we have a diamond ifcvt the fallthough block will have a branch at the end of it that disappears when predicated, so discount it from the predication cost. Differential Revision: https://reviews.llvm.org/D34952 llvm-svn: 307788
* [mips][mt] Add missing files from last commitSimon Dardis2017-07-122-0/+104
| | | | llvm-svn: 307779
* [mips][mt][3/7] Add IAS support for emt, dmt instructions.Simon Dardis2017-07-124-2/+21
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35250 llvm-svn: 307774
* [ARM] GlobalISel: Simplify inst selector code. NFCDiana Picus2017-07-121-198/+143
| | | | | | | | | | | Refactor CmpHelper into something simpler. It was overkill to use templates for this - instead, use a simple CmpConstants structure to hold the opcodes and other constants that are different when selecting int / float / double comparisons. Also, extract some of the helpers that were in CmpHelper into ARMInstructionSelector and make use of some of them when selecting other things than just compares. llvm-svn: 307766
* [ARM] GlobalISel: Select s64 G_FCMPDiana Picus2017-07-121-3/+38
| | | | | | | Very similar to how we select s32 G_FCMP, the only thing that is different is the exact opcodes that we use. llvm-svn: 307763
* Fully fix the movw/movt addend.Rafael Espindola2017-07-1114-30/+29
| | | | | | | | | | The issue is not if the value is pcrel. It is whether we have a relocation or not. If we have a relocation, the static linker will select the upper bits. If we don't have a relocation, we have to do it. llvm-svn: 307730
* Enhance synchscope representationKonstantin Zhuravlyov2017-07-113-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | OpenCL 2.0 introduces the notion of memory scopes in atomic operations to global and local memory. These scopes restrict how synchronization is achieved, which can result in improved performance. This change extends existing notion of synchronization scopes in LLVM to support arbitrary scopes expressed as target-specific strings, in addition to the already defined scopes (single thread, system). The LLVM IR and MIR syntax for expressing synchronization scopes has changed to use *syncscope("<scope>")*, where <scope> can be "singlethread" (this replaces *singlethread* keyword), or a target-specific name. As before, if the scope is not specified, it defaults to CrossThread/System scope. Implementation details: - Mapping from synchronization scope name/string to synchronization scope id is stored in LLVM context; - CrossThread/System and SingleThread scopes are pre-defined to efficiently check for known scopes without comparing strings; - Synchronization scope names are stored in SYNC_SCOPE_NAMES_BLOCK in the bitcode. Differential Revision: https://reviews.llvm.org/D21723 llvm-svn: 307722
* [CodeGen] Rename DEBUG_TYPE to match passnamesEvandro Menezes2017-07-119-9/+9
| | | | | | | | | Rename missing DEBUG_TYPE "machine-scheduler" from backend files, which were absent from https://reviews.llvm.org/rL303921. Differential revision: https://reviews.llvm.org/D35231 llvm-svn: 307719
* [mips][mt] Correct spelling error in comment. NFCI.Simon Dardis2017-07-111-1/+1
| | | | llvm-svn: 307717
* [mips][mt][2/7] Implement .module and .set directives for the MT ASE.Simon Dardis2017-07-113-0/+82
| | | | | | | | | | | | This patch implements the .module and .set directives for the MT ASE, notably that .module sets the relevant flags in .MIPS.abiflags and .set doesn't. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35249 llvm-svn: 307716
* [ARM, ELF] Don't shift movt relocation offsetsMartin Storsjo2017-07-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For ELF, a movw+movt pair is handled as two separate relocations. If an offset should be applied to the symbol address, this offset is stored as an immediate in the instruction (as opposed to stored as an offset in the relocation itself). Even though the actual value stored in the movt immediate after linking is the top half of the value, we need to store the unshifted offset prior to linking. When the relocation is made during linking, the offset gets added to the target symbol value, and the upper half of the value is stored in the instruction. This makes sure that movw+movt with offset symbols get properly handled, in case the offset addition in the lower half should be carried over to the upper half. This makes the output from the additions to the test case match the output from GNU binutils. For COFF and MachO, the movw/movt relocations are handled as a pair, and the overflow from the lower half gets carried over to the movt, so they should keep the shifted offset just as before. Differential Revision: https://reviews.llvm.org/D35242 llvm-svn: 307713
* [AArch64] Remove unused IsDarwin & IsNotDarwin predicates (NFCI). Florian Hahn2017-07-111-3/+0
| | | | | | | | | | | | Reviewers: t.p.northover, rengolin Reviewed By: t.p.northover Subscribers: aemerson, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D35266 llvm-svn: 307706
* [mips][mt][1/7] Add the MT ASE as a subtarget feature.Simon Dardis2017-07-115-1/+13
| | | | | | | | | | Preparatory work for adding the MIPS MT (multi-threading) ASE instructions. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35247 llvm-svn: 307679
* Revert "AMDGPU: Do not test for SI in getIsaVersion"Konstantin Zhuravlyov2017-07-111-1/+1
| | | | | | | | This reverts commit r307573. This breaks downstream test. llvm-svn: 307678
* [Hexagon] Do not rely on callee-saved info in hasFPKrzysztof Parzyszek2017-07-112-14/+9
| | | | llvm-svn: 307675
* [PPC] Fix two bugs in frame lowering.Tony Jiang2017-07-112-17/+26
| | | | | | | | | | | 1. The available program storage region of the red zone to compilers is 288 bytes rather than 244 bytes. 2. The formula for negative number alignment calculation should be y = x & ~(n-1) rather than y = (x + (n-1)) & ~(n-1). Differential Revision: https://reviews.llvm.org/D34337 llvm-svn: 307672
* [Hexagon] Add support for nontemporal loads and stores on HVXKrzysztof Parzyszek2017-07-114-15/+112
| | | | | | | | Patch by Michael Wu. Differential Revision: https://reviews.llvm.org/D35104 llvm-svn: 307671
* fix formatting; NFCHiroshi Inoue2017-07-111-2/+2
| | | | llvm-svn: 307662
* [SystemZ] Minor fixing in SystemZScheduleZ13.tdJonas Paulsson2017-07-111-69/+84
| | | | | | | Some minor corrections for the recently added instructions. Review: Ulrich Weigand llvm-svn: 307658
* [ARM] GlobalISel: Add reg mapping for s64 G_FCMPDiana Picus2017-07-111-5/+9
| | | | | | Map the result into GPR and the operands into FPR. llvm-svn: 307653
* [ARM] ldr pc,=expression should be allowed in Thumb2Peter Smith2017-07-111-1/+1
| | | | | | | | | | | This change allows the pc to be used as a destination register for the pseudo instruction LDR pc,=expression . The pseudo instruction must not be transformed into a MOV, but it can use the Thumb2 LDR (literal) instruction to a constant pool entry. See (A7.7.43 from ARMv7M ARM ARM). Differential Revision: https://reviews.llvm.org/D34751 llvm-svn: 307640
* [ARM] GlobalISel: Fix oversight in G_FCMP legalizationDiana Picus2017-07-111-0/+1
| | | | | | | We used to forget to erase the original instruction when replacing a G_FCMP true/false. Fix this bug and make sure the tests check for it. llvm-svn: 307639
* [globalisel][tablegen] Correct matching of intrinsic ID's.Daniel Sanders2017-07-111-4/+4
| | | | | | | | | | | | TreePatternNode considers them to be plain integers but MachineInstr considers them to be a distinct kind of operand. The tweak to AArch64InstrInfo.td to produce a simple test case is a NFC for everything except GlobalISelEmitter (confirmed by diffing the tablegenerated files). GlobalISelEmitter is currently unable to infer the type of operands in the Dst pattern from the operands in the Src pattern. llvm-svn: 307634
* [ARM] GlobalISel: Legalize s64 G_FCMPDiana Picus2017-07-112-9/+64
| | | | | | Same as the s32 version, for both hard and soft float. llvm-svn: 307633
* [GlobalISel][X86] Use correct AND instructions.Igor Breger2017-07-111-1/+1
| | | | | | AND8ri8 not supported in 64bit. llvm-svn: 307630
* [PowerPC] fix latency for simple integer instructions in POWER9 schedulerHiroshi Inoue2017-07-111-1/+1
| | | | | | | | | In the POWER9 instruction scheduler, SchedWriteRes for the simple integer instructions are misconfigured to use that of (costly) DFU instructions. This results in surprisingly long instruction latency estimation and causes misbehavior in some optimizers such as if-conversion. Differential Revision: https://reviews.llvm.org/D34869 llvm-svn: 307624
* [PowerPC] avoid redundant analysis while lowering an immediate; NFCHiroshi Inoue2017-07-111-2/+8
| | | | | | | | | | This patch reduces compilation time by avoiding redundant analysis while selecting instructions to create an immediate. If the instruction count required to create the input number without rotate is 2, we do not need further analysis to find a shorter instruction sequence with rotate; rotate + load constant cannot be done by 1 instruction (i.e. getInt64CountDirectnever return 0). This patch should not change functionality. Differential Revision: https://reviews.llvm.org/D34986 llvm-svn: 307623
* [AVR] Remove a few very old TODOs that don't have enough context to understandDylan McKay2017-07-112-3/+4
| | | | llvm-svn: 307622
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