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* AVX-512: Fixed extract_vector_elt for v8i1 vectorElena Demikhovsky2014-03-024-6/+14
| | | | llvm-svn: 202624
* Switch all uses of LLVM_OVERRIDE to just use 'override' directly.Craig Topper2014-03-0247-312/+282
| | | | llvm-svn: 202621
* Switch all uses of LLVM_FINAL to just use 'final', and remove the macro.Craig Topper2014-03-026-6/+6
| | | | llvm-svn: 202618
* [Sparc] Add support for parsing branches and conditional move instructions ↵Venkatraman Govindaraju2014-03-024-44/+89
| | | | | | with %fcc1-%fcc3 conditional registers. llvm-svn: 202616
* [Sparc] Make floating point branch instruction formats to accept %fcc0-%fcc1 ↵Venkatraman Govindaraju2014-03-024-34/+40
| | | | | | | | conditional registers as input. No functionality change. llvm-svn: 202614
* [Sparc] Add support for parsing fcmp with %fcc registers.Venkatraman Govindaraju2014-03-028-12/+78
| | | | llvm-svn: 202610
* [Sparc] Add register class for floating point conditional flags (%fcc0 - %fcc3).Venkatraman Govindaraju2014-03-023-11/+16
| | | | llvm-svn: 202604
* [SparcV9] Add support for parsing branch instructions with prediction.Venkatraman Govindaraju2014-03-017-44/+156
| | | | llvm-svn: 202602
* Remove extra truncs/exts around i32 bit operations on PPC64Hal Finkel2014-03-011-12/+82
| | | | | | | | | | | | | | | | | | | | | | | | | This generalizes the code to eliminate extra truncs/exts around i1 bit operations to also do the same on PPC64 for i32 bit operations. This eliminates a fairly prevalent code wart: int foo(int a) { return a == 5 ? 7 : 8; } On PPC64, because of the extension implied by the ABI, this would generate: cmplwi 0, 3, 5 li 12, 8 li 4, 7 isel 3, 4, 12, 2 rldicl 3, 3, 0, 32 blr where the 'rldicl 3, 3, 0, 32', the extension, is completely unnecessary. At least for the single-BB case (which is all that the DAG combine mechanism can handle), this unnecessary extension is no longer generated. llvm-svn: 202600
* [Sparc] Add support for parsing annulled branch instructions.Venkatraman Govindaraju2014-03-017-13/+80
| | | | llvm-svn: 202599
* [Sparc] Add support for parsing sparcv9 instructions addc/subc/addccc/subccc.Venkatraman Govindaraju2014-03-014-7/+13
| | | | llvm-svn: 202598
* [Sparc] Add missing ALU instruction patterns.Venkatraman Govindaraju2014-03-011-0/+35
| | | | llvm-svn: 202597
* Now that we have C++11, turn simple functors into lambdas and remove a ton ↵Benjamin Kramer2014-03-012-28/+13
| | | | | | | | of boilerplate. No intended functionality change. llvm-svn: 202588
* [Sparc] Add support to decode unimp instruction.Venkatraman Govindaraju2014-03-011-2/+2
| | | | llvm-svn: 202581
* [Sparc] Add support to decode negative simm13 operands in the sparc ↵Venkatraman Govindaraju2014-03-012-23/+36
| | | | | | disassembler. llvm-svn: 202578
* [Sparc] Add support for decoding call instructions in the sparc disassembler.Venkatraman Govindaraju2014-03-012-2/+24
| | | | llvm-svn: 202577
* [Sparc] Add support to disassemble sparc memory instructions.Venkatraman Govindaraju2014-03-013-19/+142
| | | | llvm-svn: 202575
* [Sparc] Implement writeNopData. Emit actual NOP instruction instead of just ↵Venkatraman Govindaraju2014-03-011-3/+8
| | | | | | filling with zeroes. llvm-svn: 202572
* [Sparc] Teach SparcAsmParser to emit correct relocations for PIC code.Venkatraman Govindaraju2014-03-012-3/+55
| | | | llvm-svn: 202571
* [Sparc] 80 column rule. No functionality change.Venkatraman Govindaraju2014-03-011-1/+2
| | | | llvm-svn: 202565
* [Sparc] Add support for parsing directives in SparcAsmParser.Venkatraman Govindaraju2014-03-011-2/+48
| | | | llvm-svn: 202564
* [Sparc] Emit 'restore' instead of 'restore %g0, %g0, %g0'. This improves the ↵Venkatraman Govindaraju2014-03-012-0/+11
| | | | | | readability of the generated code. llvm-svn: 202563
* R600: Verify all instructions in the AsmPrinter on debug buildsTom Stellard2014-02-281-0/+7
| | | | | | | Make a call to R600's implementation of verifyInstruction() to check that instructions are only using legal operands. llvm-svn: 202544
* R600/SI: Expand all v16[if]32 operationsTom Stellard2014-02-281-1/+1
| | | | llvm-svn: 202543
* Fixed operand of SC microMIPS instruction.Zoran Jovanovic2014-02-282-1/+5
| | | | llvm-svn: 202526
* Fixed encoding of SYSCALL microMIPS instruction.Zoran Jovanovic2014-02-281-1/+1
| | | | llvm-svn: 202523
* Revert revision 202518 because of wrong commit message.Zoran Jovanovic2014-02-281-1/+1
| | | | llvm-svn: 202521
* Fix operand of SC instruction.Zoran Jovanovic2014-02-281-1/+1
| | | | llvm-svn: 202518
* X86Operand is extracted into individual header.Evgeniy Stepanov2014-02-283-497/+533
| | | | | | | | | | X86Operand is extracted into individual header, because it allows to create an arbitrary memory operand and append it to MCInst. It'll be reused in X86 inline assembly instrumentation. Patch by Yuri Gorshenin. llvm-svn: 202496
* Reorder Mips/MCTargetDesc/CMakeLists.txt.NAKAMURA Takumi2014-02-281-1/+1
| | | | llvm-svn: 202483
* [mips] Add MipsNaClELFStreamer.cpp to CMakeLists.txt.Sasa Stankovic2014-02-281-0/+1
| | | | llvm-svn: 202482
* [mips] Implement NaCl sandboxing of indirect jumps:Sasa Stankovic2014-02-285-3/+170
| | | | | | | | | * Align targets of indirect jumps to instruction bundle boundaries (in MI layer). * Add masking instructions before indirect jumps (in MC layer). Differential Revision: http://llvm-reviews.chandlerc.com/D2847 llvm-svn: 202479
* Swap PPC isel operands to allow for 0-foldingHal Finkel2014-02-281-0/+117
| | | | | | | | | The PPC isel instruction can fold 0 into the first operand (thus eliminating the need to materialize a zero-containing register when the 'true' result of the isel is 0). When the isel is fed by a bit register operation that we can invert, do so as part of the bit-register-operation peephole routine. llvm-svn: 202469
* Trying to unbreak the darwin11 builderHal Finkel2014-02-281-0/+3
| | | | | | | | | The CR bit tracking code broke PPC/Darwin; trying to get it working again... (the darwin11 builder, which defaults to the darwin ABI when running PPC tests, asserted when running test/CodeGen/PowerPC/inverted-bool-compares.ll) llvm-svn: 202459
* Try to unbreak the C++11 buildHal Finkel2014-02-281-2/+2
| | | | | | Cannot use negative numbers in case statements without running afoul of -Wc++11-narrowing. llvm-svn: 202455
* Add CR-bit tracking to the PowerPC backend for i1 valuesHal Finkel2014-02-2820-156/+2159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change enables tracking i1 values in the PowerPC backend using the condition register bits. These bits can be treated on PowerPC as separate registers; individual bit operations (and, or, xor, etc.) are supported. Tracking booleans in CR bits has several advantages: - Reduction in register pressure (because we no longer need GPRs to store boolean values). - Logical operations on booleans can be handled more efficiently; we used to have to move all results from comparisons into GPRs, perform promoted logical operations in GPRs, and then move the result back into condition register bits to be used by conditional branches. This can be very inefficient, because the throughput of these CR <-> GPR moves have high latency and low throughput (especially when other associated instructions are accounted for). - On the POWER7 and similar cores, we can increase total throughput by using the CR bits. CR bit operations have a dedicated functional unit. Most of this is more-or-less mechanical: Adjustments were needed in the calling-convention code, support was added for spilling/restoring individual condition-register bits, and conditional branch instruction definitions taking specific CR bits were added (plus patterns and code for generating bit-level operations). This is enabled by default when running at -O2 and higher. For -O0 and -O1, where the ability to debug is more important, this feature is disabled by default. Individual CR bits do not have assigned DWARF register numbers, and storing values in CR bits makes them invisible to the debugger. It is critical, however, that we don't move i1 values that have been promoted to larger values (such as those passed as function arguments) into bit registers only to quickly turn around and move the values back into GPRs (such as happens when values are returned by functions). A pair of target-specific DAG combines are added to remove the trunc/extends in: trunc(binary-ops(binary-ops(zext(x), zext(y)), ...) and: zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...) In short, we only want to use CR bits where some of the i1 values come from comparisons or are used by conditional branches or selects. To put it another way, if we can do the entire i1 computation in GPRs, then we probably should (on the POWER7, the GPR-operation throughput is higher, and for all cores, the CR <-> GPR moves are expensive). POWER7 test-suite performance results (from 10 runs in each configuration): SingleSource/Benchmarks/Misc/mandel-2: 35% speedup MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown MultiSource/Applications/lemon/lemon: 8% slowdown llvm-svn: 202451
* Provide a target override for the latest regalloc heuristic.Andrew Trick2014-02-272-0/+7
| | | | | | | This is a temporary workaround for native arm linux builds: PR18996: Changing regalloc order breaks "lencod" on native arm linux builds. llvm-svn: 202433
* Lower FNEG just like FABS to fneg[ds] and fmov[ds], thus avoidingRoman Divacky2014-02-271-17/+8
| | | | | | | expensive libcall. Also, Qp_neg is not implemented on at least FreeBSD. This is also what gcc is doing. llvm-svn: 202422
* Debug info: Remove ARMAsmPrinter::EmitDwarfRegOp(). AsmPrinter can nowAdrian Prantl2014-02-272-68/+0
| | | | | | | | | | scan the register file for sub- and super-registers. No functionality change intended. (Tests are updated because the comments in the assembler output are different.) llvm-svn: 202416
* [XCore] Support functions returning more than 4 words.Richard Osborne2014-02-275-22/+125
| | | | | | | | | | If a function returns a large struct by value return the first 4 words in registers and the rest on the stack in a location reserved by the caller. This is needed to support the xC language which supports functions returning an arbitrary number of return values. This is r202397 reapplied with a fix to avoid an uninitialized read of a member. llvm-svn: 202414
* [XCore] Make LowerCallResult a static function.Richard Osborne2014-02-272-33/+24
| | | | | | No functionality change. This is r202396 reapplied with no changes. llvm-svn: 202413
* Remove MCPureStreamer.Rafael Espindola2014-02-271-2/+0
| | | | | | | We moved MCJIT to use native object formats a long time ago and R600 now uses ELF, so it was dead. llvm-svn: 202408
* Revert r202396, r202397.Richard Osborne2014-02-275-137/+44
| | | | | | These are causing test failures, revert for now. llvm-svn: 202398
* [XCore] Support functions returning more than 4 words.Richard Osborne2014-02-275-22/+124
| | | | | | | | | | | | | | | | | | Summary: If a function returns a large struct by value return the first 4 words in registers and the rest on the stack in a location reserved by the caller. This is needed to support the xC language which supports functions returning an arbitrary number of return values. Reviewers: robertlytton Reviewed By: robertlytton CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2889 llvm-svn: 202397
* [XCore] Make LowerCallResult a static function.Richard Osborne2014-02-272-33/+24
| | | | | | No functionality change. llvm-svn: 202396
* [XCore] Target optimized library function __memcpy_4()Richard Osborne2014-02-272-0/+42
| | | | | | | | | | | | | | | | Summary: If the src, dst and size of a memcpy are known to be 4 byte aligned we can call __memcpy_4() instead of memcpy(). Reviewers: robertlytton Reviewed By: robertlytton CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2871 llvm-svn: 202395
* [XCore] Add dag combines for instructions that ignore some input bits.Richard Osborne2014-02-271-0/+42
| | | | | | | These instructions ignore the high bits of one of their input operands - try and use this to simplify the code. llvm-svn: 202394
* [XCore] Provide information about known zero bits of resource instructions.Richard Osborne2014-02-271-0/+28
| | | | llvm-svn: 202393
* [X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODSCraig Topper2014-02-272-29/+49
| | | | llvm-svn: 202348
* [X86] Add RAX/EAX/AX Uses/Defs to XCHG RAX/EAX/AX instructions.Craig Topper2014-02-271-0/+4
| | | | llvm-svn: 202347
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