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* Add definition of WSBH (Word Swap Bytes within Halfwords), which is anAkira Hatanaka2011-12-202-8/+10
| | | | | | | | | | instruction supported by mips32r2, and add a pattern which replaces bswap with a ROTR and WSBH pair. WSBW is removed since it is not an instruction the current architectures support. llvm-svn: 147015
* 64-bit uint-fp conversion nodes are expanded.Akira Hatanaka2011-12-201-0/+2
| | | | llvm-svn: 147014
* Enable custom lowering DYNAMIC_STACKALLOC nodes.Akira Hatanaka2011-12-201-0/+1
| | | | llvm-svn: 147013
* Set the correct stack pointer register that should be saved or restored.Akira Hatanaka2011-12-201-1/+1
| | | | llvm-svn: 147012
* ARM .req register name aliases are case insensitive, just like regnames.Jim Grosbach2011-12-201-3/+4
| | | | llvm-svn: 147009
* Add function MipsDAGToDAGISel::SelectMULT and factor out code that generatesAkira Hatanaka2011-12-201-37/+47
| | | | | | | nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU nodes. llvm-svn: 147008
* Fix indentation.Akira Hatanaka2011-12-201-115/+115
| | | | llvm-svn: 147007
* 64-bit data directive.Akira Hatanaka2011-12-201-1/+1
| | | | llvm-svn: 147005
* 32-to-64-bit sext_inreg pattern.Akira Hatanaka2011-12-201-0/+5
| | | | llvm-svn: 147004
* Add 64-bit extload patterns.Akira Hatanaka2011-12-201-2/+12
| | | | llvm-svn: 147003
* Add patterns for matching extloads with 64-bit address. The patterns are enabledAkira Hatanaka2011-12-201-5/+13
| | | | | | only when the target ABI is N64. llvm-svn: 147001
* Move comment to appropriate place.Jim Grosbach2011-12-201-1/+1
| | | | llvm-svn: 147000
* Add code in MipsDAGToDAGISel for selecting constant +0.0.Akira Hatanaka2011-12-201-0/+6
| | | | | | MIPS64 can generate constant +0.0 with a single DMTC1 instruction. llvm-svn: 146999
* Heed spill slot alignment on ARM.Jakob Stoklund Olesen2011-12-202-3/+4
| | | | | | | | | | | Use the spill slot alignment as well as the local variable alignment to determine when the stack needs to be realigned. This works now that the ARM target can always realign the stack by using a base pointer. Still respect the ARMBaseRegisterInfo::canRealignStack() function vetoing a realigned stack. Don't use aligned spill code in that case. llvm-svn: 146997
* Revert part of r146995 that was accidentally commmitted.Akira Hatanaka2011-12-201-6/+0
| | | | llvm-svn: 146996
* 32-to-64-bit sign extension pattern.Akira Hatanaka2011-12-202-0/+8
| | | | llvm-svn: 146995
* Add a pattern for matching zero-store with 64-bit address. The pattern is ↵Akira Hatanaka2011-12-201-1/+4
| | | | | | | | enabled only when the target ABI is N64. llvm-svn: 146992
* ARM assembly parsing and encoding for VST2 single-element, double spaced.Jim Grosbach2011-12-202-37/+129
| | | | llvm-svn: 146990
* ARM assembly parsing and encoding for VLD2 single-element, double spaced.Jim Grosbach2011-12-202-43/+171
| | | | llvm-svn: 146983
* ARM target code clean up. Check for iOS, not Darwin where it makes sense.Evan Cheng2011-12-207-78/+79
| | | | llvm-svn: 146981
* First steps in ARM AsmParser support for .eabi_attribute and .archJason W Kim2011-12-201-0/+18
| | | | | | | (Both used for Linux gnueabi) No behavioral change yet (no tests need so far) llvm-svn: 146977
* This is the second fix related to VZEXT_MOVL node.Elena Demikhovsky2011-12-201-1/+6
| | | | | | | | | | | | | | | | | | | | The failure that I see in the current version is: LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14] 0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13] 0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12] 0x18b9870: v4i64 = undef [ID=4] 0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10] 0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9970: i32 = Constant<0> [ID=3] 0x18b9170: v2i64 = undef [ORD=1] [ID=1] 0x18b9570: i32 = Constant<2> [ID=5] llvm-svn: 146975
* Begin teaching the X86 target how to efficiently codegen patterns thatChandler Carruth2011-12-202-6/+17
| | | | | | | | | | | | | | | use the zero-undefined variants of CTTZ and CTLZ. These are just simple patterns for now, there is more to be done to make real world code using these constructs be optimized and codegen'ed properly on X86. The existing tests are spiffed up to check that we no longer generate unnecessary cmov instructions, and that we generate the very important 'xor' to transform bsr which counts the index of the most significant one bit to the number of leading (most significant) zero bits. Also they now check that when the variant with defined zero result is used, the cmov is still produced. llvm-svn: 146974
* Fix up the CMake build for the new files added in r146960, they'reChandler Carruth2011-12-2011-0/+11
| | | | | | likely to stay either way that discussion ends up resolving itself. llvm-svn: 146966
* Unweaken vtables as per ↵David Blaikie2011-12-2069-18/+309
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.Bob Wilson2011-12-201-2/+5
| | | | | | | | | | | | We used to rely on the *eh_sjlj_setjmp instructions to mark that a function with setjmp/longjmp exception handling clobbers all the registers. But with the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are expanded away earlier, before PEI can see them to determine what registers to save and restore. Mark the dispatchsetup instruction in the same way, since that instruction cannot be expanded early. This also more accurately reflects when the registers are clobbered. llvm-svn: 146949
* ARM assembly shifts by zero should be plain 'mov' instructions.Jim Grosbach2011-12-201-0/+17
| | | | | | | | | | "mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's not strictly legal UAL syntax. It's a common extension and the friendly thing to do. rdar://10604663 llvm-svn: 146937
* Add basic generic CodeGen support for half.Dan Gohman2011-12-201-0/+4
| | | | llvm-svn: 146927
* ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.Jim Grosbach2011-12-192-0/+45
| | | | | | | | e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117" rdar://10603913 llvm-svn: 146925
* ARM assembly parsing and encoding support for LDRD(label).Jim Grosbach2011-12-195-3/+72
| | | | | | rdar://9932658 llvm-svn: 146921
* Add patterns for matching immediates whose lower 16-bit is cleared. TheseAkira Hatanaka2011-12-192-0/+10
| | | | | | patterns emit a single LUi instruction instead of a pair of LUi and ORi. llvm-svn: 146900
* Tidy up. Simplify logic. No functional change intended.Akira Hatanaka2011-12-1910-132/+117
| | | | llvm-svn: 146896
* ARM NEON two-operand aliases for VPADD.Jim Grosbach2011-12-191-0/+10
| | | | | | rdar://10602276 llvm-svn: 146895
* Remove definitions of double word shift plus 32 instructions. Assembler orAkira Hatanaka2011-12-191-21/+9
| | | | | | | direct-object emitter should emit the appropriate shift instruction depending on the shift amount. llvm-svn: 146893
* ARM VFP pre-UAL mnemonic aliases for fmul[sd].Jim Grosbach2011-12-192-1/+4
| | | | llvm-svn: 146892
* Remove unused predicate.Akira Hatanaka2011-12-191-3/+0
| | | | llvm-svn: 146889
* Remove the restriction on the first operand of the add node in SelectAddr.Akira Hatanaka2011-12-191-3/+1
| | | | | | | | | | | | | | | | | | This change reduces the number of instructions generated. For example, (load (add (sub $n0, $n1), (MipsLo got(s)))) results in the following sequence of instructions: 1. sub $n2, $n0, $n1 2. lw got(s)($n2) Previously, three instructions were needed. 1. sub $n2, $n0, $n1 2. addiu $n3, $n2, got(s) 3. lw 0($n3) llvm-svn: 146888
* ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].Jim Grosbach2011-12-192-1/+5
| | | | llvm-svn: 146887
* ARM NEON implied destination aliases for VMAX/VMIN.Jim Grosbach2011-12-191-0/+62
| | | | llvm-svn: 146885
* ARM NEON relax parse time diagnostics for alignment specifiers.Jim Grosbach2011-12-193-9/+11
| | | | | | | There's more variation that we need to handle. Error checking will need to be on operand predicates. llvm-svn: 146884
* Tidy up.Jim Grosbach2011-12-191-7/+7
| | | | llvm-svn: 146882
* Remove a register class that can just as well be synthesized.Jakob Stoklund Olesen2011-12-191-8/+0
| | | | | | | Add the new TableGen register class synthesizer feature to the release notes. llvm-svn: 146875
* Emit a getMatchingSuperRegClass() implementation for every target.Jakob Stoklund Olesen2011-12-194-226/+6
| | | | | | | | | Use information computed while inferring new register classes to emit accurate, table-driven implementations of getMatchingSuperRegClass(). Delete the old manual, error-prone implementations in the targets. llvm-svn: 146873
* Another variadics tweak.Benjamin Kramer2011-12-181-4/+3
| | | | llvm-svn: 146852
* Use the fancy new VariadicFunction template instead of a plain variadic ↵Benjamin Kramer2011-12-181-34/+33
| | | | | | | | function. Some compilers were complaining about passing StringRef to it. llvm-svn: 146850
* Hexagon: Remove unused variables.Benjamin Kramer2011-12-182-13/+0
| | | | llvm-svn: 146846
* Remove an unused X86ISD node type.Craig Topper2011-12-173-3/+0
| | | | llvm-svn: 146833
* X86: Factor the bswap asm matching to be slightly less horrible to read.Benjamin Kramer2011-12-171-74/+63
| | | | llvm-svn: 146831
* Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.Evan Cheng2011-12-171-4/+7
| | | | llvm-svn: 146805
* Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added theRafael Espindola2011-12-172-1/+5
| | | | | | asm parsing and testcase. llvm-svn: 146801
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