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* Whitespace.NAKAMURA Takumi2013-05-151-2/+2
| | | | llvm-svn: 181906
* Support unaligned load/store on more ARM targetsDerek Schuff2013-05-151-4/+17
| | | | | | | | | | | | | | | | | This patch matches GCC behavior: the code used to only allow unaligned load/store on ARM for v6+ Darwin, it will now allow unaligned load/store for v6+ Darwin as well as for v7+ on other targets. The distinction is made because v6 doesn't guarantee support (but LLVM assumes that Apple controls hardware+kernel and therefore have conformant v6 CPUs), whereas v7 does provide this guarantee (and Linux behaves sanely). Overall this should slightly improve performance in most cases because of reduced I$ pressure. Patch by JF Bastien llvm-svn: 181897
* [PowerPC] Remove need for adjustFixupOffst hackUlrich Weigand2013-05-153-24/+10
| | | | | | | | | | | | | | | | Now that applyFixup understands differently-sized fixups, we can define fixup_ppc_lo16/fixup_ppc_lo16_ds/fixup_ppc_ha16 to properly be 2-byte fixups, applied at an offset of 2 relative to the start of the instruction text. This has the benefit that if we actually need to generate a real relocation record, its address will come out correctly automatically, without having to fiddle with the offset in adjustFixupOffset. Tested on both 64-bit and 32-bit PowerPC, using external and integrated assembler. llvm-svn: 181894
* [SystemZ] Make use of SUBTRACT HALFWORDRichard Sandiford2013-05-151-0/+1
| | | | | | Thanks to Ulrich Weigand for noticing that this instruction was missing. llvm-svn: 181893
* [PowerPC] Correctly handle fixups of other than 4 byte sizeUlrich Weigand2013-05-151-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | The PPCAsmBackend::applyFixup routine handles the case where a fixup can be resolved within the same object file. However, this routine is currently hard-coded to assume the size of any fixup is always exactly 4 bytes. This is sort-of correct for fixups on instruction text; even though it only works because several of what really would be 2-byte fixups are presented as 4-byte fixups instead (requiring another hack in PPCELFObjectWriter::adjustFixupOffset to clean it up). However, this assumption breaks down completely for fixups on data, which legitimately can be of any size (1, 2, 4, or 8). This patch makes applyFixup aware of fixups of varying sizes, introducing a new helper routine getFixupKindNumBytes (along the lines of what the ARM back end does). Note that in order to handle fixups of size 8, we also need to fix the return type of adjustFixupValue to uint64_t to avoid truncation. Tested on both 64-bit and 32-bit PowerPC, using external and integrated assembler. llvm-svn: 181891
* [SystemZ] Add more future work items to the READMERichard Sandiford2013-05-151-7/+91
| | | | | | Based on an analysis by Ulrich Weigand. llvm-svn: 181882
* ARM ISel: Don't create illegal types during LowerMULArnold Schwaighofer2013-05-141-25/+32
| | | | | | | | | | | | | | | | | The transformation happening here is that we want to turn a "mul(ext(X), ext(X))" into a "vmull(X, X)", stripping off the extension. We have to make sure that X still has a valid vector type - possibly recreate an extension to a smaller type. In case of a extload of a memory type smaller than 64 bit we used create a ext(load()). The problem with doing this - instead of recreating an extload - is that an illegal type is exposed. This patch fixes this by creating extloads instead of ext(load()) sequences. Fixes PR15970. radar://13871383 llvm-svn: 181842
* Implement the PowerPC system call (sc) instruction.Bill Schmidt2013-05-144-0/+28
| | | | | | Instruction added at request of Roman Divacky. Tested via asm-parser. llvm-svn: 181821
* Hexagon: Pass to replace tranfer/copy instructions into combine instructionJyotsna Verma2013-05-145-0/+686
| | | | | | where possible. llvm-svn: 181817
* Reapply "Subtract isn't commutative, fix this for MMX psub." withEric Christopher2013-05-141-7/+7
| | | | | | | a somewhat randomly chosen cpu that will minimize cpu specific differences on bots. llvm-svn: 181814
* Temporarily revert "Subtract isn't commutative, fix this for MMX psub."Eric Christopher2013-05-141-7/+7
| | | | | | It's causing failures on the atom bot. llvm-svn: 181812
* Subtract isn't commutative, fix this for MMX psub.Eric Christopher2013-05-141-7/+7
| | | | | | Patch by Andrea DiBiagio. llvm-svn: 181809
* Hexagon: Add patterns to generate 'combine' instructions.Jyotsna Verma2013-05-141-0/+87
| | | | llvm-svn: 181805
* Hexagon: ArePredicatesComplement should not restrict itself to TFRs.Jyotsna Verma2013-05-141-5/+31
| | | | llvm-svn: 181803
* PPC32: Fix stack collision between FP and CR save areas.Bill Schmidt2013-05-141-0/+1
| | | | | | | | | | | | | | | | | The changes to CR spill handling missed a case for 32-bit PowerPC. The code in PPCFrameLowering::processFunctionBeforeFrameFinalized() checks whether CR spill has occurred using a flag in the function info. This flag is only set by storeRegToStackSlot and loadRegFromStackSlot. spillCalleeSavedRegisters does not call storeRegToStackSlot, but instead produces MI directly. Thus we don't see the CR is spilled when assigning frame offsets, and the CR spill ends up colliding with some other location (generally the FP slot). This patch sets the flag in spillCalleeSavedRegisters for PPC32 so that the CR spill is properly detected and gets its own slot in the stack frame. llvm-svn: 181800
* Hexagon: Remove dead-code after unconditional return from addPreSched2.Jyotsna Verma2013-05-141-3/+0
| | | | llvm-svn: 181797
* R600/SI: Add processor type for Hainan asicTom Stellard2013-05-142-1/+3
| | | | | | | | | | Patch by: Alex Deucher Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181792
* [SystemZ] Add disassembler supportRichard Sandiford2013-05-1411-6/+399
| | | | llvm-svn: 181777
* [SystemZ] Rework handling of constant PC-relative operandsRichard Sandiford2013-05-143-20/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GNU assembler treats things like: brasl %r14, 100 in the same way as: brasl %r14, .+100 rather than as a branch to absolute address 100. We implemented this in LLVM by creating an immediate operand rather than the usual expr operand, and by handling immediate operands specially in the code emitter. This was undesirable for (at least) three reasons: - the specialness of immediate operands was exposed to the backend MC code, rather than being limited to the assembler parser. - in disassembly, an immediate operand really is an absolute address. (Note that this means reassembling printed disassembly can't recreate the original code.) - it would interfere with any assembly manipulation that we might try in future. E.g. operations like branch shortening can change the relative position of instructions, but any code that updates sym+offset addresses wouldn't update an immediate "100" operand in the same way as an explicit ".+100" operand. This patch changes the implementation so that the assembler creates a "." label for immediate PC-relative operands, so that the operand to the MCInst is always the absolute address. The patch also adds some error checking of the offset. llvm-svn: 181773
* [SystemZ] Remove bogus isAsmParserOnlyRichard Sandiford2013-05-141-28/+22
| | | | | | | | | | Marking instructions as isAsmParserOnly stops them from being disassembled. However, in cases where separate asm and codegen versions exist, we actually want to disassemble to the asm ones. No functional change intended. llvm-svn: 181772
* [SystemZ] Match operands to fields by name rather than by orderRichard Sandiford2013-05-143-57/+79
| | | | | | | | | | | | | | | | | | | | | | | | The SystemZ port currently relies on the order of the instruction operands matching the order of the instruction field lists. This isn't desirable for disassembly, where the two are matched only by name. E.g. the R1 and R2 fields of an RR instruction should have corresponding R1 and R2 operands. The main complication is that addresses are compound operands, and as far as I know there is no mechanism to allow individual suboperands to be selected by name in "let Inst{...} = ..." assignments. Luckily it doesn't really matter though. The SystemZ instruction encoding groups all address fields together in a predictable order, so it's just as valid to see the entire compound address operand as a single field. That's the approach taken in this patch. Matching by name in turn means that the operands to COPY SIGN and CONVERT TO FIXED instructions can be given in natural order. (It was easier to do this at the same time as the rename, since otherwise the intermediate step was too confusing.) No functional change intended. llvm-svn: 181771
* [SystemZ] Match operands to fields by name rather than by orderRichard Sandiford2013-05-145-312/+326
| | | | | | | | | | | | | | | | | | | | | | | | The SystemZ port currently relies on the order of the instruction operands matching the order of the instruction field lists. This isn't desirable for disassembly, where the two are matched only by name. E.g. the R1 and R2 fields of an RR instruction should have corresponding R1 and R2 operands. The main complication is that addresses are compound operands, and as far as I know there is no mechanism to allow individual suboperands to be selected by name in "let Inst{...} = ..." assignments. Luckily it doesn't really matter though. The SystemZ instruction encoding groups all address fields together in a predictable order, so it's just as valid to see the entire compound address operand as a single field. That's the approach taken in this patch. Matching by name in turn means that the operands to COPY SIGN and CONVERT TO FIXED instructions can be given in natural order. (It was easier to do this at the same time as the rename, since otherwise the intermediate step was too confusing.) No functional change intended. llvm-svn: 181769
* Fix typo.Reed Kotler2013-05-141-1/+1
| | | | llvm-svn: 181759
* Removed an unnamed namespace and forgot to make two of the functions insideReed Kotler2013-05-141-3/+5
| | | | | | "static". llvm-svn: 181754
* This is the first of three patches which creates stubs used forReed Kotler2013-05-141-0/+275
| | | | | | | | | | | | | | | | | | | | | | | Mips16/32 floating point interoperability. When Mips16 code calls external functions that would normally have some of its parameters or return values passed in floating point registers, it needs (Mips32) helper functions to do this because while in Mips16 mode there is no ability to access the floating point registers. In Pic mode, this is done with a set of predefined functions in libc. This case is already handled in llvm for Mips16. In static relocation mode, for efficiency reasons, the compiler generates stubs that the linker will use if it turns out that the external function is a Mips32 function. (If it's Mips16, then it does not need the helper stubs). These stubs are identically named and the linker knows about these tricks and will not create multiple copies and will delete them if they are not needed. llvm-svn: 181753
* Mips assembler: Assembler macro ADDIU $rs,immJack Carter2013-05-131-1/+2
| | | | | | | | | | | | | | This patch adds alias for addiu instruction which enables following syntax: addiu $rs,imm The macro is translated as: addiu $rs,$rs,imm Contributer: Vladimir Medic llvm-svn: 181729
* Fix goofy commentary in PPCTargetObjectFile.cpp.Bill Schmidt2013-05-131-2/+2
| | | | llvm-svn: 181725
* PPC64: Constant initializers with dynamic relocations go in .data.rel.ro.Bill Schmidt2013-05-134-0/+94
| | | | | | | | | | | | | | | | | | | | | This fixes warning messages observed in the oggenc application test in projects/test-suite. Special handling is needed for the 64-bit PowerPC SVR4 ABI when a constant is initialized with a pointer to a function in a shared library. Because a function address is implemented as the address of a function descriptor, the use of copy relocations can lead to problems with initialization. GNU ld therefore replaces copy relocations with dynamic relocations to be resolved by the dynamic linker. This means the constant cannot reside in the read-only data section, but instead belongs in .data.rel.ro, which is designed for constants containing dynamic relocations. The implementation creates a class PPC64LinuxTargetObjectFile inheriting from TargetLoweringObjectFileELF, which behaves like its parent except to place constants of this sort into .data.rel.ro. The test case is reduced from the oggenc application. llvm-svn: 181723
* [mips] Add option -mno-ldc1-sdc1.Akira Hatanaka2013-05-133-4/+75
| | | | | | | | This option is used when the user wants to avoid emitting double precision FP loads and stores. Double precision FP loads and stores are expanded to single precision instructions after register allocation. llvm-svn: 181718
* [mips] Define a helper function which creates an instruction with the sameAkira Hatanaka2013-05-132-0/+19
| | | | | | operands as the prototype instruction but with a different opcode. llvm-svn: 181714
* [mips] Rename functions. No functionality changes.Akira Hatanaka2013-05-137-29/+29
| | | | llvm-svn: 181713
* Remove unused fields and arguments.Rafael Espindola2013-05-133-13/+6
| | | | llvm-svn: 181706
* The purpose of the patch is to fix the syntax of ARM mrc and mrc2 ↵Mihai Popa2013-05-134-11/+43
| | | | | | instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. llvm-svn: 181705
* Correctly preserve the input chain for potential tailcall nodes whoseLang Hames2013-05-131-1/+1
| | | | | | | | | | | | return values are bitcasts. The chain had previously been being clobbered with the entry node to the dag, which sometimes caused other code in the function to be erroneously deleted when tailcall optimization kicked in. <rdar://problem/13827621> llvm-svn: 181696
* Suppress GCC compiler warnings in release builds about variables that are onlyDuncan Sands2013-05-132-0/+2
| | | | | | read in asserts. llvm-svn: 181689
* Remove the MachineMove class.Rafael Espindola2013-05-1322-35/+59
| | | | | | | | | | | | It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. llvm-svn: 181680
* Change getFrameMoves to return a const reference.Rafael Espindola2013-05-118-54/+42
| | | | | | | To add a frame now there is a dedicated addFrameMove which also takes care of constructing the move itself. llvm-svn: 181657
* Checkin in of first of several patches to finish implementation ofReed Kotler2013-05-1012-16/+282
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
* Fix unused variable error.Jyotsna Verma2013-05-101-2/+1
| | | | | | | Earlier, this variable was used in an assert and was causing failure on darwin. llvm-svn: 181630
* Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore.Jyotsna Verma2013-05-104-707/+81
| | | | | | No functionality change. llvm-svn: 181628
* Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.Jyotsna Verma2013-05-108-703/+170
| | | | llvm-svn: 181624
* Fix the R600 build.Rafael Espindola2013-05-102-3/+2
| | | | llvm-svn: 181621
* [ms-inline asm] Fix a crasher when we fail on a direct match.Chad Rosier2013-05-102-6/+9
| | | | | | | | | | | | | | | | | | The issue was that the MatchingInlineAsm and VariantID args to the MatchInstructionImpl function weren't being set properly. Specifically, when parsing intel syntax, the parser thought it was parsing inline assembly in the at&t dialect; that will never be the case. The crash was caused when the emitter tried to emit the instruction, but the operands weren't set. When parsing inline assembly we only set the opcode, not the operands, which is used to lookup the instruction descriptor. rdar://13854391 and PR15945 Also, this commit reverts r176036. Now that we're correctly parsing the intel syntax the pushad/popad don't match properly. I've reimplemented that fix using a MnemonicAlias. llvm-svn: 181620
* Remove unused argument.Rafael Espindola2013-05-1023-33/+27
| | | | llvm-svn: 181618
* Remove unused function.Rafael Espindola2013-05-102-11/+0
| | | | llvm-svn: 181606
* Implement AsmParser for ARM unwind directives.Logan Chien2013-05-102-27/+284
| | | | | | | | | | | | | | | | | | | This commit implements the AsmParser for fnstart, fnend, cantunwind, personality, handlerdata, pad, setfp, save, and vsave directives. This commit fixes some minor issue in the ARMELFStreamer: * The switch back to corresponding section after the .fnend directive. * Emit the unwind opcode while processing .fnend directive if there is no .handlerdata directive. * Emit the unwind opcode to .ARM.extab while processing .handlerdata even if .personality directive does not exist. llvm-svn: 181603
* R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen ↵Tom Stellard2013-05-105-1217/+12
| | | | | | | | | | | | | | patterns The BFE optimization was the only one we were actually using, and it was emitting an intrinsic that we don't support. https://bugs.freedesktop.org/show_bug.cgi?id=64201 Reviewed-by: Christian König <christian.koenig@amd.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181580
* R600: Expand SUB for v2i32/v4i32Tom Stellard2013-05-101-0/+2
| | | | | | | | | | Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181579
* R600: Expand MUL for v4i32/v2i32Tom Stellard2013-05-101-0/+2
| | | | | | | | | | | | Fixes piglit test for OpenCL builtin mul24, and allows mad24 to run. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181578
* R600: Expand SRA for v4i32/v2i32Tom Stellard2013-05-101-0/+2
| | | | | | | | | | | | v2: Add v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181577
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