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* R600: Expand vselect for v4i32 and v2i32Tom Stellard2013-05-101-0/+3
| | | | | | | | | | | | v2: Add vselect v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181576
* [x86AsmParser] It's valid to stop parsing an operand at an immediate.Chad Rosier2013-05-091-1/+3
| | | | | | rdar://13854369 and PR15944 llvm-svn: 181564
* Generate a compact unwind encoding in the face of a stack alignment push.Bill Wendling2013-05-091-0/+6
| | | | | | | | | | | | | We generate a `push' of a random register (%rax) if the stack needs to be aligned by the size of that register. However, this could mess up compact unwind generation. In particular, we want to still generate compact unwind in the presence of this monstrosity. Check if the push of of the %rax/%eax register. If it is and it's marked with the `FrameSetup' flag, then we can generate a compact unwind encoding for the function only if the push is the last FrameSetup instruction. llvm-svn: 181540
* Hexagon: Remove switch cases from GetDotNewPredOp and isPostIncrement functions.Jyotsna Verma2013-05-093-593/+46
| | | | | | No functionality change. llvm-svn: 181535
* Hexagon: Use relation map for getMatchingCondBranchOpcode() and Jyotsna Verma2013-05-091-535/+5
| | | | | | getInvertedPredicatedOpcode() functions instead of switch cases. llvm-svn: 181530
* Simplify the code a bit.Bill Wendling2013-05-091-19/+10
| | | | | | | | | | The compact unwind registers were defined in two different places. It's better just to place them in the function that uses them and specify that this is a 64-bit or 32-bit machine. No functionality change. llvm-svn: 181529
* [XCore] Fix handling of functions where only the LR is spilled.Richard Osborne2013-05-091-27/+30
| | | | | | | | | | | | | | Previously we only checked if the LR required saving if the frame size was non zero. However because the caller reserves 1 word for the callee to use that doesn't count towards our frame size it is possible for the LR to need saving and for the frame size to be 0. We didn't hit when the LR needed saving because of a function calls because the 1 word of stack we must allocate for our callee means the frame size is always non zero in this case. However we can hit this case if the LR is clobbered in inline asm. llvm-svn: 181520
* [mips] Add instruction selection pattern for (seteq $LHS, 0).Akira Hatanaka2013-05-081-0/+2
| | | | llvm-svn: 181459
* Remove unused isLegalAddressImmediate() method.Roman Divacky2013-05-082-21/+0
| | | | llvm-svn: 181452
* [PowerPC] Fix regression in generating @ha/@l relocsUlrich Weigand2013-05-081-1/+10
| | | | | | | | | | | | | | | | The patch I committed as revision 167864 introduced a regression that causes LLVM to no longer generate appropriate relocs for @ha/@l symbol references (but fail an assertion instead). This is fixed here by re-enabling support for the VK_PPC_GAS_HA16/ VK_PPC_GAS_LO16 variant kinds (and their Darwin variants) in PPCELFObjectWriter.cpp. Tested by running projects/test-suite in -m32 mode with the integrated assembler forced on. A standalone test case will be committed shortly as well. llvm-svn: 181450
* Fix handling of anonymous aggregate parameters for powerpc*-apple-darwin8.Bill Schmidt2013-05-081-4/+4
| | | | | | | | This fixes bug 15821 similarly to the powerpc64-linux fix for bug 14779. Patch by David Fang. llvm-svn: 181449
* For r181148: fixed warning 'enumeral and non-enumeral type in conditional ↵Stepan Dyatkovskiy2013-05-081-1/+1
| | | | | | expression'. llvm-svn: 181437
* PPCInstrInfo::optimizeCompareInstr should not optimize FP comparesHal Finkel2013-05-081-18/+11
| | | | | | | | The floating-point record forms on PPC don't set the condition register bits based on a comparison with zero (like the integer record forms do), but rather based on the exception status bits. llvm-svn: 181423
* Corrected Atom latencies for SSE SQRT instructions.Preston Gurd2013-05-073-19/+36
| | | | llvm-svn: 181346
* Hexagon: Fix Small Data support to handle -G 0 correctly.Jyotsna Verma2013-05-077-2/+199
| | | | llvm-svn: 181344
* Cleanup PPCInstrInfo::optimizeCompareInstrHal Finkel2013-05-071-14/+10
| | | | | | | Implement suggestions by Bill Schmidt in post-commit review. No functionality change intended. llvm-svn: 181338
* Reverting r181331.Jyotsna Verma2013-05-076-196/+3
| | | | | | Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt. llvm-svn: 181334
* Hexagon: Fix Small Data support to handle -G 0 correctly.Jyotsna Verma2013-05-076-3/+196
| | | | llvm-svn: 181331
* Hexagon: Set accessSize and addrMode on all load/store instructions.Jyotsna Verma2013-05-074-68/+125
| | | | llvm-svn: 181324
* Re-enable AVX detection on x64 platforms.Michael Kuperstein2013-05-071-1/+2
| | | | llvm-svn: 181313
* [SystemZ] Fix InitMCCodeGenInfo callRichard Sandiford2013-05-071-2/+2
| | | | | | | | createSystemZMCCodeGenInfo was not passing the optimization level to InitMCCodeGenInfo(), so -O0 would be ignored. Fixes DebugInfo/namespace.ll after the changes in r181271. llvm-svn: 181312
* R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcodeTom Stellard2013-05-062-1/+14
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181269
* R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemaskTom Stellard2013-05-061-1/+1
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181268
* R600/SI: Add intrinsic for texture image loadingTom Stellard2013-05-063-10/+46
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181267
* R600/SI: Add pattern for uint_to_fpTom Stellard2013-05-061-1/+3
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181266
* R600/SI: Add patterns for integer maxima / minimaTom Stellard2013-05-061-4/+12
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181265
* R600/SI: Add pattern for AMDGPU.trunc intrinsicTom Stellard2013-05-061-1/+3
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 181263
* Print IR from Hexagon MI passes with -print-before/after-all.Krzysztof Parzyszek2013-05-066-17/+79
| | | | llvm-svn: 181255
* Cleanup of the HexagonTargetMachine setup.Krzysztof Parzyszek2013-05-061-29/+34
| | | | llvm-svn: 181250
* Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.Jyotsna Verma2013-05-066-407/+307
| | | | llvm-svn: 181235
* Make references to HexagonTargetMachine "const".Krzysztof Parzyszek2013-05-066-25/+26
| | | | llvm-svn: 181233
* R600: Remove dead code from the CodeEmitter v2Tom Stellard2013-05-063-400/+64
| | | | | | | | | v2: - Replace switch statement with TSFlags query Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181229
* R600: Emit config values in register / value pairsTom Stellard2013-05-062-3/+55
| | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181228
* R600: Stop emitting the instruction type byte before each instructionTom Stellard2013-05-061-33/+2
| | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181225
* R600: Emit ISA for CALL_FS_* instructionsTom Stellard2013-05-061-1/+0
| | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181223
* [SystemZ] Add back endUlrich Weigand2013-05-0662-1/+10763
| | | | | | | | | | | | | | This adds the actual lib/Target/SystemZ target files necessary to implement the SystemZ target. Note that at this point, the target cannot yet be built since the configure bits are missing. Those will be provided shortly by a follow-on patch. This version of the patch incorporates feedback from reviews by Chris Lattner and Anton Korobeynikov. Thanks to all reviewers! Patch by Richard Sandiford. llvm-svn: 181203
* [PowerPC] Fix memory corruption in AsmParserUlrich Weigand2013-05-061-7/+7
| | | | | | | | As pointed out by Evgeniy Stepanov, assigning a std::string temporary to a StringRef is not a good idea. Rework MatchRegisterName to avoid using the .lower routine. llvm-svn: 181192
* ARM AnalyzeBranch should conservatively return true when it sees a predicatedEvan Cheng2013-05-051-3/+9
| | | | | | | | | | indirect branch at the end of the BB. Otherwise if-converter, branch folding pass may incorrectly update its successor info if it consider BB as fallthrough to the next BB. rdar://13782395 llvm-svn: 181161
* [XCore] Add LDAPB instructions.Richard Osborne2013-05-051-3/+13
| | | | | | | With the change the disassembler now supports the XCore ISA in its entirety. llvm-svn: 181155
* [XCore] Update LDAP to use pcrel_imm.Richard Osborne2013-05-051-3/+3
| | | | llvm-svn: 181154
* [XCore] Rename calltarget -> pcrel_imm.Richard Osborne2013-05-051-6/+6
| | | | | | No functionality change. llvm-svn: 181153
* [XCore] Add BLRB instructions.Richard Osborne2013-05-051-0/+7
| | | | llvm-svn: 181152
* [XCore] Remove '-' from back branch asm syntax.Richard Osborne2013-05-052-6/+18
| | | | | | | | Instead operands are treated as negative immediates where the sign bit is implicit in the instruction encoding. llvm-svn: 181151
* For ARM backend, fixed "byval" attribute support.Stepan Dyatkovskiy2013-05-052-33/+104
| | | | | | | | | | | | | | | | | | | | | | | Now even the small structures could be passed within byval (small enough to be stored in GPRs). In regression tests next function prototypes are checked: PR15293: %artz = type { i32 } define void @foo(%artz* byval %s) define void @foo2(%artz* byval %s, i32 %p, %artz* byval %s2) foo: "s" stored in R0 foo2: "s" stored in R0, "s2" stored in R2. Next AAPCS rules are checked: 5.5 Parameters Passing, C.4 and C.5, "ParamSize" is parameter size in 32bit words: -- NSAA != 0, NCRN < R4 and NCRN+ParamSize > R4. Parameter should be sent to the stack; NCRN := R4. -- NSAA != 0, and NCRN < R4, NCRN+ParamSize < R4. Parameter stored in GPRs; NCRN += ParamSize. llvm-svn: 181148
* Remove a recently redundant transform from X86ISelLowering.David Majnemer2013-05-051-11/+0
| | | | | | | | | | | | X86ISelLowering has support to treat: (icmp ne (and (xor %flags, -1), (shl 1, flag)), 0) as if it were actually: (icmp eq (and %flags, (shl 1, flag)), 0) However, r179386 has code at the InstCombine level to handle this. llvm-svn: 181145
* Add ArrayRef constructor from None, and do the cleanups that this ↵Dmitri Gribenko2013-05-052-4/+4
| | | | | | | | constructor enables Patch by Robert Wilhelm. llvm-svn: 181138
* whitespaceNadav Rotem2013-05-041-2/+2
| | | | llvm-svn: 181137
* Fix an odd comment.Nadav Rotem2013-05-041-2/+1
| | | | llvm-svn: 181136
* AArch64: enable MCJIT and tests now that everything passes.Tim Northover2013-05-041-1/+1
| | | | | | | This removes dire warnings about AArch64 being unsupported and enables the tests when appropriate on this platform. llvm-svn: 181135
* AArch64: implement first relocation required for MCJITTim Northover2013-05-041-0/+6
| | | | | | | | | | | R_AARCH64_PCREL32 is present in even trivial .eh_frame sections and so is required to compile any function without the "nounwind" attribute. This change implements very basic infrastructure in the RuntimeDyldELF file and allows (for example) the test-shift.ll MCJIT test to pass on AArch64. llvm-svn: 181131
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