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* R600: Use DAG lowering pass to handle fcos/fsinVincent Lejeune2013-07-094-23/+52
| | | | | NOTE: This is a candidate for the stable branch. llvm-svn: 185940
* R600: Print Export SwizzleVincent Lejeune2013-07-091-2/+2
| | | | llvm-svn: 185939
* Add MC assembly/disassembly support for VRINT{A, N, P, M} to V8FP.Joey Gouly2013-07-093-3/+59
| | | | llvm-svn: 185929
* Add MC assembly/disassembly support for VRINT{Z, X, R} to V8FP.Joey Gouly2013-07-091-0/+21
| | | | llvm-svn: 185926
* [PowerPC] Support ".machine any"Ulrich Weigand2013-07-091-0/+27
| | | | | | | | | | | | The PowerPC assembler is supposed to provide a directive .machine that allows switching the supported CPU instruction set on the fly. Since we do not yet check CPU feature sets at all and always accept any available instruction, this is not really useful at this point. However, it makes sense to accept (and ignore) ".machine any" to avoid spuriously rejecting existing assembler files that use this. llvm-svn: 185924
* Add MC assembly/disassembly support for VCVT{A, N, P, M} to V8FP.Joey Gouly2013-07-093-6/+86
| | | | llvm-svn: 185922
* [SystemZ] Use MVC for simple load/store pairsRichard Sandiford2013-07-094-0/+86
| | | | | | | | | | | | Look for patterns of the form (store (load ...), ...) in which the two locations are known not to partially overlap. (Identical locations are OK.) These sequences are better implemented by MVC unless either the load or the store could use RELATIVE LONG instructions. The testcase showed that we weren't using LHRL and LGHRL for extload16, only sextloadi16. The patch fixes that too. llvm-svn: 185919
* [SystemZ] Use "STC;MVC" for memsetRichard Sandiford2013-07-093-0/+95
| | | | | | | | | | | | Use "STC;MVC" for memsets that are too big for two STCs or MV...Is yet small enough for a single MVC. As with memcpy, I'm leaving longer cases till later. The number of tests might seem excessive, but f33 & f34 from memset-04.ll failed the first cut because I'd not added the "?:" on the calculation of Size1. llvm-svn: 185918
* [PowerPC] Support .llong and fix .wordUlrich Weigand2013-07-091-1/+3
| | | | | | | | This adds support for the .llong PowerPC-specifc assembler directive. In doing so, I notices that .word is currently incorrect: it is supposed to define a 2-byte data element, not a 4-byte one. llvm-svn: 185911
* PPC: Allocate RS spill slot for unaligned i64 load/storeHal Finkel2013-07-091-2/+33
| | | | | | | | | | | | | | | | | | | This fixes another bug found by llvm-stress! If we happen to be doing an i64 load or store into a stack slot that has less than a 4-byte alignment, then the frame-index elimination may need to use an indexed load or store instruction (because the offset may not be a multiple of 4, a requirement of the STD/LD instructions). The extra register needed to hold the offset comes from the register scavenger, and it is possible that the scavenger will need to use an emergency spill slot. As a result, we need to make sure that a spill slot is allocated when doing an i64 load/store into a less-than-4-byte-aligned stack slot. Because test cases for things like this tend to be fairly fragile, I've concatenated a few small bugpoint-reduced test cases together to form the regression test. llvm-svn: 185907
* X86: Add comment.Jim Grosbach2013-07-091-0/+5
| | | | llvm-svn: 185900
* X86 fast-isel: Avoid explicit AH subreg reference for [SU]Rem.Jim Grosbach2013-07-091-4/+31
| | | | | | | | | | | | | Explicit references to %AH for an i8 remainder instruction can lead to references to %AH in a REX prefixed instruction, which causes things to blow up. Do the same thing in FastISel as we do for DAG isel and instead shift %AX right by 8 bits and then extract the 8-bit subreg from that result. rdar://14203849 http://llvm.org/bugs/show_bug.cgi?id=16105 llvm-svn: 185899
* [PowerPC] Always use "assembler dialect" 1Ulrich Weigand2013-07-089-42/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A setting in MCAsmInfo defines the "assembler dialect" to use. This is used by common code to choose between alternatives in a multi-alternative GNU inline asm statement like the following: __asm__ ("{sfe|subfe} %0,%1,%2" : "=r" (out) : "r" (in1), "r" (in2)); The meaning of these dialects is platform specific, and GCC defines those for PowerPC to use dialect 0 for old-style (POWER) mnemonics and 1 for new-style (PowerPC) mnemonics, like in the example above. To be compatible with inline asm used with GCC, LLVM ought to do the same. Specifically, this means we should always use assembler dialect 1 since old-style mnemonics really aren't supported on any current platform. However, the current LLVM back-end uses: AssemblerDialect = 1; // New-Style mnemonics. in PPCMCAsmInfoDarwin, and AssemblerDialect = 0; // Old-Style mnemonics. in PPCLinuxMCAsmInfo. The Linux setting really isn't correct, we should be using new-style mnemonics everywhere. This is changed by this commit. Unfortunately, the setting of this variable is overloaded in the back-end to decide whether or not we are on a Darwin target. This is done in PPCInstPrinter (the "SyntaxVariant" is initialized from the MCAsmInfo AssemblerDialect setting), and also in PPCMCExpr. Setting AssemblerDialect to 1 for both Darwin and Linux no longer allows us to make this distinction. Instead, this patch uses the MCSubtargetInfo passed to createPPCMCInstPrinter to distinguish Darwin targets, and ignores the SyntaxVariant parameter. As to PPCMCExpr, this patch adds an explicit isDarwin argument that needs to be passed in by the caller when creating a target MCExpr. (To do so this patch implicitly also reverts commit 184441.) llvm-svn: 185858
* PPC: Mark vector CC action for SETO and SETONE as ExpandHal Finkel2013-07-081-0/+3
| | | | | | | | Another bug found by llvm-stress! This fixes hitting llvm_unreachable("Invalid integer vector compare condition"); at the end of getVCmpInst in PPCISelDAGToDAG. llvm-svn: 185855
* Add a comment to this change, requested by Eric Christopher.Joey Gouly2013-07-081-0/+4
| | | | llvm-svn: 185853
* ARM: Improve codegen for generic vselect.Jim Grosbach2013-07-081-0/+18
| | | | | | | | Fall back to by-element insert rather than building it up on the stack. rdar://14351991 llvm-svn: 185846
* PPC: Mark vector FREM as Expand by defaultHal Finkel2013-07-081-0/+1
| | | | | | | Another bug found by llvm-stress! This fixes crashing with: LLVM ERROR: Cannot select: v4f32 = frem ... llvm-svn: 185840
* [PowerPC] Support time base instructionsUlrich Weigand2013-07-081-0/+6
| | | | | | | | This adds support for the old-style time base instructions; while new programs are supposed to use mfspr, the mftb instructions are still supported and in use by existing assembler files. llvm-svn: 185829
* [PowerPC] Support basic compare mnemonicsUlrich Weigand2013-07-083-0/+43
| | | | | | | | | | | | | | | | | This adds support for the basic mnemoics (with the L operand) for the fixed-point compare instructions. These are defined as aliases for the already existing CMPW/CMPD patterns, depending on the value of L. This requires use of InstAlias patterns with immediate literal operands. To make this work, we need two further changes: - define a RegisterPrefix, because otherwise literals 0 and 1 would be parsed as literal register names - provide a PPCAsmParser::validateTargetOperandClass routine to recognize immediate literals (like ARM does) llvm-svn: 185826
* [PowerPC] Fix PR16556 (handle undef ppcf128 in LowerFP_TO_INT).Bill Schmidt2013-07-081-0/+9
| | | | | | | | | | | | | | | | | | | | | PPCTargetLowering::LowerFP_TO_INT() expects its source operand to be either an f32 or f64, but this is not checked. A long double (ppcf128) operand will normally be custom-lowered to a conversion to f64 in this context. However, this isn't the case for an UNDEF node. This patch recognizes a ppcf128 as a legal source operand for FP_TO_INT only if it's an undef, in which case it creates an undef of the target type. At some point we might want to do a wholesale custom lowering of ISD::UNDEF when the type is ppcf128, but it's not really clear that's a great idea, and probably more work than it's worth for a situation that only arises in the case of a programming error. At this point I think simple is best. The test case comes from PR16556, and is a crash-test only. llvm-svn: 185821
* Reuse %rax after calling __chkstk on win64Nico Rieck2013-07-082-7/+9
| | | | | | Reapply this as I reverted the wrong commit. llvm-svn: 185807
* Revert "Proper va_arg/va_copy lowering on win64"Nico Rieck2013-07-081-3/+1
| | | | | | | | This reverts commit 2b52880592a525cfe04d8f9008a35da8c2ea94c3. Needs review. llvm-svn: 185806
* [SystemZ] Remove unwanted part from last commitRichard Sandiford2013-07-081-2/+0
| | | | | | | I was originally going to use MVC for memmove too, but that's less of a clear win. Remove some accidental left-overs in the previous commit. llvm-svn: 185804
* [SystemZ] Use MVC for memcpyRichard Sandiford2013-07-089-2/+145
| | | | | | | Use MVC for memcpy in cases where a single MVC is enough. Using MVC is a win for longer copies too, but I'll leave that for later. llvm-svn: 185802
* Revert "Reuse %rax after calling __chkstk on win64"Nico Rieck2013-07-082-9/+7
| | | | | | This reverts commit 01f8d579f7672872324208ac5bc4ac311e81b22e. llvm-svn: 185781
* Reuse %rax after calling __chkstk on win64Nico Rieck2013-07-072-7/+9
| | | | llvm-svn: 185778
* Add MC support for the v8fp instructions: vmaxnm and vminnm.Joey Gouly2013-07-063-8/+27
| | | | llvm-svn: 185767
* Proper va_arg/va_copy lowering on win64Nico Rieck2013-07-061-1/+3
| | | | llvm-svn: 185763
* ARM: Add a pack pattern for matching arithmetic shift rightArnold Schwaighofer2013-07-051-0/+3
| | | | llvm-svn: 185714
* ARM: Fix incorrect pack patternArnold Schwaighofer2013-07-051-2/+4
| | | | | | | | | | | A "pkhtb x, x, y asr #num" uses the lower 16 bits of "y asr #num" and packs them in the bottom half of "x". An arithmetic and logic shift are only equivalent in this context if the shift amount is 16. We would be shifting in ones into the bottom 16bits instead of zeros if "y" is negative. radar://14338767 llvm-svn: 185712
* [SystemZ] Remove no-op MVCsRichard Sandiford2013-07-052-0/+27
| | | | | | | | | | | The stack coloring pass has code to delete stores and loads that become trivially dead after coloring. Extend it to cope with single instructions that copy from one frame index to another. The testcase happens to show an example of this kicking in at the moment. It did occur in Real Code too though. llvm-svn: 185705
* [SystemZ] Remove redundant frame MMOsRichard Sandiford2013-07-051-24/+4
| | | | | | | | | | This fixes foldMemoryOperandImpl() so that it doesn't create duplicated frame MMOs. I hadn't realized when writing r185434 that it was the caller's responsibility to add these. No behavioural change intended. llvm-svn: 185704
* [SystemZ] Enable the use of MVC for frame-to-frame spillsRichard Sandiford2013-07-051-10/+2
| | | | | | | | | | ...now that the problem that prompted the restriction has been fixed. The original spill-02.py was a compromise because at the time I couldn't find an example that actually failed without the two scavenging slots. The version included here did. llvm-svn: 185701
* [PowerPC] Add some special @got@tprel fixup casesUlrich Weigand2013-07-051-0/+20
| | | | | | | | | | | | | | | When a target@got@tprel or target@got@tprel@l symbol variant is used in a fixup_ppc_half16 (*not* fixup_ppc_half16ds) context, we currently fail, since the corresponding R_PPC64_GOT_TPREL16 / R_PPC64_GOT_TPREL16_LO relocation types do not exist. However, since such symbol variants resolve to GOT offsets which are always 4-aligned, we can simply instead use the _DS variants of the relocation types, which *do* exist. The same applies for the @got@dtprel variants. llvm-svn: 185700
* [SystemZ] Allocate a second register scavenging slotRichard Sandiford2013-07-051-2/+6
| | | | | | | | | | | | | This is another prerequisite for frame-to-frame MVC copies. I'll commit the patch that makes use of the slot separately. The downside of trying to test many corner cases with each of the available addressing modes is that a fair few tests need to account for the new frame layout. I do still think it's useful to have all these tests though, since it's something that wouldn't get much coverage otherwise. llvm-svn: 185698
* [SystemZ] Clean up register scavenging codeRichard Sandiford2013-07-054-57/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | SystemZ wants normal register scavenging slots, as close to the stack or frame pointer as possible. The only reason it was using custom code was because PrologEpilogInserter assumed an x86-like layout, where the frame pointer is at the opposite end of the frame from the stack pointer. This meant that when frame pointer elimination was disabled, the slots ended up being as close as possible to the incoming stack pointer, which is the opposite of what we want on SystemZ. This patch adds a new knob to say which layout is used and converts SystemZ to use target-independent scavenging slots. It's one of the pieces needed to support frame-to-frame MVCs, where two slots might be required. The ABI requires us to allocate 160 bytes for calls, so one approach would be to use that area as temporary spill space instead. It would need some surgery to make sure that the slot isn't live across a call though. I stuck to the "isFPCloseToIncomingSP - ..." style comment on the "do what the surrounding code does" principle. The FP case is already covered by several Systemz/frame-* tests, which fail without the PrologueEpilogueInserter change, so no new ones are needed. No behavioural change intended. llvm-svn: 185696
* [PowerPC] Support @tls in the asm parserUlrich Weigand2013-07-059-22/+70
| | | | | | | | | | | | | | | | | | This adds support for the last missing construct to parse TLS-related assembler code: add 3, 4, symbol@tls The ADD8TLS currently hard-codes the @tls into the assembler string. This cannot be handled by the asm parser, since @tls is parsed as a symbol variant. This patch changes ADD8TLS to have the @tls suffix printed as symbol variant on output too, which allows us to remove the isCodeGenOnly marker from ADD8TLS. This in turn means that we can add a AsmOperand to accept @tls marked symbols on input. As a side effect, this means that the fixup_ppc_tlsreg fixup type is no longer necessary and can be merged into fixup_ppc_nofixup. llvm-svn: 185692
* PR16490: fix a crash in ARMDAGToDAGISel::SelectInlineAsm.Joey Gouly2013-07-051-0/+6
| | | | | | | | | | | In the SelectionDAG immediate operands to inline asm are constructed as two separate operands. The first is a constant of value InlineAsm::Kind_Imm and the second is a constant with the value of the immediate. In ARMDAGToDAGISel::SelectInlineAsm, if we reach an operand of Kind_Imm we should skip over the next operand too. llvm-svn: 185688
* Use a OwningPtr instead of a manual delete.Rafael Espindola2013-07-041-5/+3
| | | | llvm-svn: 185673
* Fix leak. Should bring back the valgrind bot.Rafael Espindola2013-07-041-0/+1
| | | | llvm-svn: 185663
* [PowerPC] Implement writeNopDataUlrich Weigand2013-07-041-4/+8
| | | | | | | | | | | This implements a proper PPCAsmBackend::writeNopData routine that actually writes PowerPC nop instructions. This fixes the last remaining difference in object file output (text section) between the integrated assembler and GNU as that I've seen anywhere. llvm-svn: 185662
* Remove an unneeded call to 'UpdateThumbVFPPredicate', spotted by Amaury.Joey Gouly2013-07-041-1/+0
| | | | llvm-svn: 185651
* Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} ↵Joey Gouly2013-07-044-2/+94
| | | | | | | | | instructions. This adds a new decoder table/namespace 'VFPV8', as these instructions have their top 4 bits as 0b1111, while other Thumb instructions have 0b1110. llvm-svn: 185642
* [PowerPC] Add all trap mnemonicsUlrich Weigand2013-07-041-0/+31
| | | | | | | This adds support for all basic and extended variants of the trap instructions to the asm parser. llvm-svn: 185638
* [PowerPC] Add asm parser support for CR expressionsUlrich Weigand2013-07-042-5/+84
| | | | | | | | This adds support for specifying condition registers and condition register fields via expressions using the symbols defined by the PowerISA, like "4*cr2+eq". llvm-svn: 185633
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-047-29/+0
| | | | | | These exception-related opcodes are not used any longer. llvm-svn: 185625
* Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.Joey Gouly2013-07-042-1/+57
| | | | llvm-svn: 185620
* Add a space between closing template '>' to unbreak build.Craig Topper2013-07-041-3/+3
| | | | llvm-svn: 185607
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-047-15/+15
| | | | | | specifying the vector size. llvm-svn: 185606
* Revert r185595-185596 which broke buildbots.Jakob Stoklund Olesen2013-07-047-0/+29
| | | | | | | Revert "Simplify landing pad lowering." Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes." llvm-svn: 185600
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