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* [mips][microMIPS] Implement BREAK16 and SDBBP16 instructionsJozef Kolek2014-11-272-0/+17
| | | | | | | | Patch by Radovan Obradovic. Differential Revision: http://reviews.llvm.org/D5048 llvm-svn: 222900
* [mips] Add synci instruction.Daniel Sanders2014-11-273-1/+56
| | | | | | | | | | | | | | Patch by Amaury Pouly Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6421 llvm-svn: 222899
* [mips][microMIPS] Implement disassembler support for 16-bit instructions ↵Jozef Kolek2014-11-272-3/+69
| | | | | | | | LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 Differential Revision: http://reviews.llvm.org/D6419 llvm-svn: 222887
* Stop uppercasing build attribute data.Charlie Turner2014-11-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The string data for string-valued build attributes were being unconditionally uppercased. There is no mention in the ARM ABI addenda about case conventions, so it's technically implementation defined as to whether the data are capitialised in some way or not. However, there are good reasons not to captialise the data. * It's less work. * Some vendors may legitimately have case-sensitive checks for these attributes which would fail on LLVM generated object files. * There could be locale issues with uppercasing. The original reasons for uppercasing appear to have stemmed from an old codesourcery toolchain behaviour, see http://comments.gmane.org/gmane.comp.compilers.llvm.cvs/87133 This patch makes the object file emitted no longer captialise string data, it encodes as seen in the assembly source. Change-Id: Ibe20dd6e60d2773d57ff72a78470839033aa5538 llvm-svn: 222882
* R600/SI: Use ZeroOrNegativeOneBooleanContentMatt Arsenault2014-11-262-2/+3
| | | | | | | | | | | | | | This sort of doesn't matter since the setcc type is i1, but this previously was using the default UndefinedBooleanContent. This makes it more consistent with R600. This enables more optimizations which typically give up on UndefinedBooleanContent. For example, there is already a special case target DAG combine for setcc + sext which can be eliminated in favor of what the generic DAG combiner can do if it assumes boolean values are sign extended. Since -1 is an inline immediate, using it is basically free and the backend already uses it when a boolean value is needed in a wider type. llvm-svn: 222850
* [Hexagon] Adding cmp* immediate form instructions.Colin LeMahieu2014-11-264-62/+68
| | | | llvm-svn: 222849
* [mips][microMIPS] Implement disassembler support for 16-bit instructions ↵Jozef Kolek2014-11-263-4/+67
| | | | | | | | LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
* [Hexagon] Adding and64, or64, and xor64 instructions.Colin LeMahieu2014-11-261-0/+13
| | | | llvm-svn: 222846
* R600/SI: Create e64 versions of and/or/xor in SILowerI1CopiesMatt Arsenault2014-11-261-3/+3
| | | | | | | | | This fixes moving boolean constants into registers before operating on them. They get permuted and shrunk down to e32 anyway later. This is a temporary fix until the patch that removes these pseudos is committed. llvm-svn: 222844
* Update AArch64 ELF relocations to ABI 1.0Will Newton2014-11-261-1/+1
| | | | | | | | | | | | | | | | | | | | This mostly entails adding relocations, however there are a couple of changes to existing relocations: 1. R_AARCH64_NONE is defined to be zero rather than 256 R_AARCH64_NONE has been defined to be zero for a long time elsewhere e.g. binutils and glibc since the submission of the AArch64 port in 2012 so this is required for compatibility. 2. R_AARCH64_TLSDESC_ADR_PAGE renamed to R_AARCH64_TLSDESC_ADR_PAGE21 I don't think there is any way for relocation names to leak out of LLVM so this should not break anything. Tested with check-all with no regressions. llvm-svn: 222821
* AVX-512: Scalar ERI intrinsicsElena Demikhovsky2014-11-264-60/+103
| | | | | | | | | | | | including SAE mode and memory operand. Added AVX512_maskable_scalar template, that should cover all scalar instructions in the future. The main difference between AVX512_maskable_scalar<> and AVX512_maskable<> is using X86select instead of vselect. I need it, because I can't create vselect node for MVT::i1 mask for scalar instruction. http://reviews.llvm.org/D6378 llvm-svn: 222820
* Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.Craig Topper2014-11-2634-298/+298
| | | | llvm-svn: 222801
* [X86][SSE] Improvements to byte shift shuffle matchingSimon Pilgrim2014-11-251-20/+20
| | | | | | | | Since (v)pslldq / (v)psrldq instructions resolve to a single input argument it is useful to match it much earlier than we currently do - this prevents more complicated shuffles (notably insertion into a zero vector) matching before it. Differential Revision: http://reviews.llvm.org/D6409 llvm-svn: 222796
* [Hexagon] Adding add64 and sub64 instructions.Colin LeMahieu2014-11-251-0/+44
| | | | llvm-svn: 222795
* Reverting 222792Colin LeMahieu2014-11-251-41/+0
| | | | llvm-svn: 222793
* [Hexagon] Adding compare with immediate instructions.Colin LeMahieu2014-11-251-0/+41
| | | | llvm-svn: 222792
* [Hexagon] Adding NOP encoding bits.Colin LeMahieu2014-11-252-5/+6
| | | | llvm-svn: 222791
* R600/SI: Only use one DEBUG()Matt Arsenault2014-11-251-2/+1
| | | | llvm-svn: 222789
* [AVX512] Add 512b integer shift by variable intrinsics and patterns.Cameron McInally2014-11-253-48/+43
| | | | llvm-svn: 222786
* [Hexagon] Adding C2_mux instruction.Colin LeMahieu2014-11-255-32/+31
| | | | llvm-svn: 222784
* Remove space before tab in all AVX512 mnemonic strings.Craig Topper2014-11-251-137/+137
| | | | llvm-svn: 222778
* [Hexagon] Replacing cmp* instructions with ones that contain encoding bits.Colin LeMahieu2014-11-255-56/+79
| | | | llvm-svn: 222771
* Revert r222746: That commit did not update any tests and caused two R600Chandler Carruth2014-11-251-2/+1
| | | | | | | | tests to start failing. Original commit log: R600/SI: Disable commutativity for MIN/MAX_LEGACY llvm-svn: 222753
* [mips][micromips] Use call instructions with short delay slotsZoran Jovanovic2014-11-251-21/+49
| | | | | | Differential Revision: http://reviews.llvm.org/D6338 llvm-svn: 222752
* R600/SI: Disable commutativity for MIN/MAX_LEGACYMarek Olsak2014-11-251-1/+2
| | | | llvm-svn: 222746
* R600/SI: Fix allocating flat_scr_lo / flat_scr_hiMatt Arsenault2014-11-251-0/+2
| | | | | | | | Only the super register flat_scr was marked as reserved, so in some cases with high register usage it would still try to allocate the subregisters. llvm-svn: 222737
* [FastISel][AArch64] Fix and extend the tbz/tbnz pattern matching.Juergen Ributzka2014-11-251-19/+20
| | | | | | | | | | The pattern matching failed to recognize all instances of "-1", because when comparing against "-1" we didn't use an APInt of the same bitwidth. This commit fixes this and also adds inverse versions of the conditon to catch more cases. llvm-svn: 222722
* [PowerPC] Add the 'attn' instructionHal Finkel2014-11-252-0/+8
| | | | | | | | The attn instruction is not part of the Power ISA, but is documented in the A2 user manual, and is accepted by the GNU assembler for the A2 and the POWER4+. Reported as part of PR21650. llvm-svn: 222712
* [PowerPC] Implement combineRepeatedFPDivisorsHal Finkel2014-11-242-0/+23
| | | | | | | | This does not matter on newer cores (where we can use reciprocal estimates in fast-math mode anyway), but for older cores this allows us to generate better fast-math code where we have multiple FDIVs with a common divisor. llvm-svn: 222710
* [AArch64] Fix clobber computation in A57LoadBalancing pass.Chad Rosier2014-11-241-1/+7
| | | | | | | Extremely difficult to reproduce, so no test case included. PR21637 llvm-svn: 222677
* Removing unused variable.Colin LeMahieu2014-11-241-1/+0
| | | | llvm-svn: 222676
* [PowerPC] Fix PR 21652 - copy st_other bits on symbol assignmentUlrich Weigand2014-11-241-0/+17
| | | | | | | | | | | When processing an assignment in the integrated assembler that sets a symbol to the value of another symbol, we need to copy the st_other bits that encode the local entry point offset. Modeled after MipsTargetELFStreamer::emitAssignment handling of the ELF::STO_MIPS_MICROMIPS flag. llvm-svn: 222672
* [Hexagon] Adding asrh instruction, removing unused multiclasses.Colin LeMahieu2014-11-242-40/+7
| | | | llvm-svn: 222670
* [Hexagon] Adding aslh instruction.Colin LeMahieu2014-11-242-5/+7
| | | | llvm-svn: 222668
* [Hexagon] Adding zxth instruction.Colin LeMahieu2014-11-242-5/+7
| | | | llvm-svn: 222662
* [Hexagon] Adding zxtb instruction.Colin LeMahieu2014-11-242-5/+43
| | | | llvm-svn: 222660
* [mips][microMIPS] Fix JRADDIUSP instructionJozef Kolek2014-11-241-1/+0
| | | | | | | | | Fix JRADDIUSP instruction, remove delay slot flag because this instruction doesn't have delay slot. Differential Revision: http://reviews.llvm.org/D6365 llvm-svn: 222658
* [mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructionsJozef Kolek2014-11-245-0/+164
| | | | | | Differential Revision: http://reviews.llvm.org/D5122 llvm-svn: 222653
* [mips][microMIPS] Implement 16-bit instructions registers including ZERO ↵Jozef Kolek2014-11-243-0/+41
| | | | | | | | | | instead of S0 Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17. Differential Revision: http://reviews.llvm.org/D5780 llvm-svn: 222652
* Removing a variable that is initialized but never read. The original author ↵Aaron Ballman2014-11-241-6/+2
| | | | | | has been alerted to the warning, in case this variable is meant to be used. Fixes -Werror builds in the meantime. llvm-svn: 222649
* [mips][microMIPS] Implement disassembler support for 16-bit instructionsJozef Kolek2014-11-242-14/+57
| | | | | | | | | | | With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
* [X86] Improved target specific combine on VSELECT dag nodes.Andrea Di Biagio2014-11-241-89/+8
| | | | | | | | | | | This patch teaches function 'transformVSELECTtoBlendVECTOR_SHUFFLE' how to convert VSELECT dag nodes to shuffles on targets that do not have SSE4.1. On pre-SSE4.1 targets, we can still perform blend operations using movss/movsd. Also, removed a target specific combine that performed a premature lowering of VSELECT nodes to target specific MOVSS/MOVSD nodes. llvm-svn: 222647
* [X86] Fixes bug in build_vector v4x32 loweringMichael Kuperstein2014-11-231-3/+6
| | | | | | | | | | | | | r222375 made some improvements to build_vector lowering of v4x32 and v4xf32 into an insertps, but it missed a case where: 1. A single extracted element is used twice. 2. The lower of the two non-zero indexes should be preserved, and the higher should be used for the dest mask. This caused a crash, since the source value for the insertps ends-up uninitialized. Differential Revision: http://reviews.llvm.org/D6377 llvm-svn: 222635
* Add missing override keywords.Craig Topper2014-11-231-2/+2
| | | | llvm-svn: 222634
* Masked Vector Load and Store Intrinsics.Elena Demikhovsky2014-11-234-4/+166
| | | | | | | | | | | | | | Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores. Added SDNodes for masked operations and lowering patterns for X86 code generator. Examples: <16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask) declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask) Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch. http://reviews.llvm.org/D6191 llvm-svn: 222632
* R600: Fix extloads of i1 on R600/EvergreenMatt Arsenault2014-11-231-0/+5
| | | | llvm-svn: 222631
* R600: Fix assert on copy of an i1 on pre-SIMatt Arsenault2014-11-231-1/+2
| | | | | | | i1 is not a legal type on Evergreen, so this combine proceeded and tried to produce a bitcast between i1 and i8. llvm-svn: 222630
* Tidied up target triple OS detection. NFCSimon Pilgrim2014-11-223-11/+6
| | | | | | Use Triple::isOS*() helper functions where possible. llvm-svn: 222622
* [x86] Teach the vector shuffle yet another step of canonicalization.Chandler Carruth2014-11-221-2/+13
| | | | | | | | No functionality changed yet, but this will prevent subsequent patches from having to handle permutations of various interleaved shuffle patterns. llvm-svn: 222614
* Fix transformation of add with pc argument to adr for non-immediateJoerg Sonnenberger2014-11-211-5/+25
| | | | | | arguments. llvm-svn: 222587
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