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* Convert gep_type_begin and gep_type_end to use ArrayRef.Jay Foad2011-07-191-1/+1
| | | | llvm-svn: 135481
* Convert TargetData::getIndexedOffset to use ArrayRef.Jay Foad2011-07-191-4/+5
| | | | llvm-svn: 135478
* Add intrinsics for the zext / sext instructions.Richard Osborne2011-07-191-7/+13
| | | | llvm-svn: 135476
* Add intrinsics for the testct, testwct instructions.Richard Osborne2011-07-191-1/+9
| | | | llvm-svn: 135475
* Add intrinsics for the peek and endin instructions.Richard Osborne2011-07-191-1/+8
| | | | llvm-svn: 135474
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-1946-273/+371
| | | | | | | (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. llvm-svn: 135468
* Make EmitAtomic functions return the correct MachineBasicBlocks so thatAkira Hatanaka2011-07-191-22/+28
| | | | | | | ExpandISelPseudos::runOnMachineFunction does not visit instructions that have just been added. llvm-svn: 135465
* Do not insert instructions in reverse order.Akira Hatanaka2011-07-191-14/+16
| | | | llvm-svn: 135464
* Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having ↵Owen Anderson2011-07-183-12/+40
| | | | | | multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler. llvm-svn: 135442
* Eliminate TargetAsmInfo::getCompactUnwindEncoding. This get rid of theEvan Cheng2011-07-181-3/+0
| | | | | | use of TargetFrameLowering in TargetAsmInfo. llvm-svn: 135439
* Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions forEvan Cheng2011-07-1829-93/+78
| | | | | | better location welcome). llvm-svn: 135438
* Mark the Darwin assembler workout as isCodeGenOnly, so that it doesn't cause ↵Owen Anderson2011-07-181-1/+1
| | | | | | decoding conflicts in the new-style disassembler. llvm-svn: 135434
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-1846-432/+341
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* Do not treat atomic.load.sub differently than other atomic binary intrinsics.Akira Hatanaka2011-07-181-12/+2
| | | | llvm-svn: 135418
* Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from Akira Hatanaka2011-07-183-85/+23
| | | | | | | | moving them out of the loop. Previously, stores and loads to a stack frame object were inserted to accomplish this. Remove the code that was needed to do this. Patch by Sasa Stankovic. llvm-svn: 135415
* Re-apply r135319 with a fix for the constant island pass.Owen Anderson2011-07-183-48/+29
| | | | | | Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change. llvm-svn: 135414
* Be more smart with VCVTSS2SD. Also place the patterns close to theBruno Cardoso Lopes2011-07-181-20/+10
| | | | | | definitions. llvm-svn: 135407
* Add AVX 128-bit sqrt versionsBruno Cardoso Lopes2011-07-181-0/+11
| | | | llvm-svn: 135404
* Change destination register operands of SC instructions so that uniqueAkira Hatanaka2011-07-181-8/+13
| | | | | | virtual registers are used. llvm-svn: 135403
* Migrate LLVM and Clang to use the new makeArrayRef(...) functions where ↵Frits van Bommel2011-07-182-14/+14
| | | | | | | | previously explicit non-default constructors were used. Mostly mechanical with some manual reformatting. llvm-svn: 135390
* land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner2011-07-1836-231/+231
| | | | llvm-svn: 135375
* Revert r135319 in an attempt to get to unbreak testers.Owen Anderson2011-07-162-27/+48
| | | | llvm-svn: 135343
* Add AVX 128-bit patterns for sint_to_fpBruno Cardoso Lopes2011-07-161-0/+20
| | | | llvm-svn: 135332
* Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and ↵Owen Anderson2011-07-152-48/+27
| | | | | | tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change. llvm-svn: 135319
* Fix a couple of things:Bruno Cardoso Lopes2011-07-151-61/+52
| | | | | | | | | | | | | | | | | | | | | | | | 1) Make non-legal 256-bit loads to be promoted to v4i64. This lets us canonize the loads and handle things the same way we use to handle for 128-bit registers. Despite of what one of the removed comments explained, the load promotion would not mess with VPERM, it's only a matter of doing the appropriate bitcasts when this instructions comes to be introduced. Also make LOAD v8i32 legal. 2) Doing 1) exposed two bugs: - v4i64 was being promoted to itself for several opcodes (introduced in r124447 by David Greene) causing endless recursion and the stack to explode. - there was no support for allOnes BUILD_VECTORs and ANDNP would fail to match because it was generating early target constant pools during lowering. 3) The testcases are already checked-in, doing 1) exposed the bugs in the current testcases. 4) Tidy up code to be more clear and explicit about AVX. llvm-svn: 135313
* Add a few patterns for 256-bit bitcasts. No testcases now, they areBruno Cardoso Lopes2011-07-151-0/+9
| | | | | | comming together with other tests. llvm-svn: 135312
* PR10370: Make sure we know how to relax push correctly on x86-64.Eli Friedman2011-07-151-0/+3
| | | | llvm-svn: 135303
* Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ↵Owen Anderson2011-07-155-19/+14
| | | | | | to simplify the path towards an auto-generated disassembler. llvm-svn: 135290
* Remove unnecessary duplicate instruction definitions that simply overloaded ↵Owen Anderson2011-07-151-9/+8
| | | | | | the type of VEXT. This can be achieved with a Pat definition, and is much more disassembler friendly. llvm-svn: 135283
* Eliminate "const" from extern const to fix breakeage since r135184 on msvc.NAKAMURA Takumi2011-07-152-2/+2
| | | | | | MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions. llvm-svn: 135269
* remove the InvalidateStructLayoutInfo API, which is dead and unnecessary nowChris Lattner2011-07-152-23/+0
| | | | | | that type refinement is toast. llvm-svn: 135245
* Remove an unnecessary header from this file. I don't think this headerChandler Carruth2011-07-151-1/+0
| | | | | | | | | | was really intended, and it may have been required prior to some of the recent refactors. Including it however causes LLVMX86Desc to need symbols from LLVMX86CodeGen, forming a dependency cycle. This was masked in almost all builds: Clang, and GCC w/ optimizations didn't actually emit the symbols! llvm-svn: 135242
* Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatestEvan Cheng2011-07-1513-27/+56
| | | | | | | solution but it is a small step towards removing the horror that is TargetAsmInfo. llvm-svn: 135237
* Major update to CMake build to reflect changes in r135219 in theChandler Carruth2011-07-1510-10/+26
| | | | | | | | | | | | backend. Moved some MCAsmInfo files down into the MCTargetDesc sublibraries, removed some (i suspect long) dead files from other parts of the CMake build, etc. Also copied the include directory hack from the Makefile. Finally, updated the lib deps. I spot checked this, and think its correct, but review appreciated there. llvm-svn: 135234
* Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng2011-07-1473-172/+224
| | | | | | MCTargetDesc to prepare for next round of changes. llvm-svn: 135219
* ARM diagnostic when 's' suffix on mnemonic that can't set flags.Jim Grosbach2011-07-141-7/+9
| | | | | | | | For example, "mlss r0, r1, r2, r3". The MLS instruction does not have a flag-setting variant. llvm-svn: 135203
* * Redo the permutation encoding for frameless stacks to be more like what theBill Wendling2011-07-141-44/+73
| | | | | | | unwind library expects. * Comment the permutation encoding for frameless stacks. llvm-svn: 135202
* Add OperandTypes for Thumb branch targets.Benjamin Kramer2011-07-141-0/+3
| | | | llvm-svn: 135199
* Port operand types for ARM and X86 over from EDIS to the .td files.Benjamin Kramer2011-07-143-1/+18
| | | | llvm-svn: 135198
* ARM MCRR/MCRR2 immediate operand range checking.Jim Grosbach2011-07-142-3/+3
| | | | llvm-svn: 135192
* ARM MCR/MCR2 assembly parsing operand constraints.Jim Grosbach2011-07-142-8/+8
| | | | | | | The immediate operands are restricted to 0-7. Enforce that when parsing assembly. llvm-svn: 135189
* After type-system-rewrite branch update the Cpp backend to not use OpaqueType.Nicolas Geoffray2011-07-141-103/+46
| | | | llvm-svn: 135186
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-14131-469/+1244
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* Check register class matching instead of width of type matchingEric Christopher2011-07-141-4/+4
| | | | | | | | | when determining validity of matching constraint. Allow i1 types access to the GR8 reg class for x86. Fixes PR10352 and rdar://9777108 llvm-svn: 135180
* Reorganize ARM assembler aliases.Jim Grosbach2011-07-141-14/+19
| | | | | | | | Consolidate the individual declarations together for ease of reference. This mirrors the organization in X86, as well, so is good for consistency. No functional change. llvm-svn: 135179
* Add 256-bit load/store recognition and matching in several places.Bruno Cardoso Lopes2011-07-142-4/+74
| | | | llvm-svn: 135171
* Don't leak operands when putting them into a shift.Benjamin Kramer2011-07-141-1/+1
| | | | llvm-svn: 135169
* Update ARM Assembly of LDM/STM.Jim Grosbach2011-07-141-5/+8
| | | | | | | ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such. Update the parsing/encoding tests accordingly. llvm-svn: 135168
* ARM ISB instruction assembly parsing.Jim Grosbach2011-07-142-3/+7
| | | | | | | The ISB instruction takes an optional operand, just like DMB/DSB. Typically only 'sy' is meaningful. llvm-svn: 135156
* Update XCoreRegisterInfo::eliminateFrameIndex() to handle DBG_VALUERichard Osborne2011-07-141-9/+17
| | | | | | instructions. llvm-svn: 135146
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