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* Move all of the x86 subtarget initialized variables down into the x86 subtargetEric Christopher2014-06-097-67/+95
| | | | | | from the x86 target machine. Should be no functional change. llvm-svn: 210479
* R600/SI: Rename VOP3 helper class to be more generalMatt Arsenault2014-06-092-4/+4
| | | | | | It has other uses besides shift instructions. llvm-svn: 210478
* [X86] Add target combine rules for horizontal add/sub.Andrea Di Biagio2014-06-091-0/+85
| | | | | | | | | | | | | | | | | | | | This patch adds new target specific combine rules to identify horizontal add/sub idioms from BUILD_VECTOR dag nodes. This patch also teaches the DAGCombiner how to canonicalize sequences of insert_vector_elt dag nodes according to the following rule: (insert_vector_elt (insert_vector_elt A, I0), I1) -> (insert_vecto_elt (insert_vector_elt A, I1), I0) This new canonicalization rule only triggers if the inner insert_vector dag node has exactly one use; also, both indices must be known constants, and I1 < I0. This last rule made it possible to write a simpler algorithm to identify horizontal add/sub patterns because now we don't have to worry about the ordering of insert_vector_elt dag nodes. llvm-svn: 210477
* R600/SI: Keep 64-bit not on SALUMatt Arsenault2014-06-093-10/+69
| | | | llvm-svn: 210476
* R600: Fix selection failure for vector bswapMatt Arsenault2014-06-091-0/+1
| | | | llvm-svn: 210475
* [PPC64LE] Generate correct little-endian code for v16i8 multiplyBill Schmidt2014-06-091-4/+16
| | | | | | | | | | | | | | | | The existing code in PPCTargetLowering::LowerMUL() for multiplying two v16i8 values assumes that vector elements are numbered in big-endian order. For little-endian targets, the vector element numbering is reversed, but the vmuleub, vmuloub, and vperm instructions still assume big-endian numbering. To account for this, we must adjust the permute control vector and reverse the order of the input registers on the vperm instruction. The existing test/CodeGen/PowerPC/vec_mul.ll is updated to be executed on powerpc64 and powerpc64le targets as well as the original powerpc (32-bit) target. llvm-svn: 210474
* [mips] Fix a bug for NaCl target - Don't report the error when non-dangerousSasa Stankovic2014-06-091-7/+6
| | | | | | | | load/store is in branch delay slot. Differential Revision: http://llvm-reviews.chandlerc.com/D4048 llvm-svn: 210470
* [X86] Avoid emitting unnecessary test instructions.Andrea Di Biagio2014-06-091-2/+19
| | | | | | | | | | | | | This patch teaches the backend how to check for the 'NoSignedWrap' flag on binary operations to improve the emission of 'test' instructions. If the result of a binary operation is known not to overflow we know that resetting the Overflow flag is unnecessary and so we can avoid emitting the test instruction. Patch by Marcello Maggioni. llvm-svn: 210468
* [X86] Use ADD/SUB instead of INC/DEC for SilvermontAlexey Volkov2014-06-096-15/+37
| | | | | | | | | | | | According to Intel Software Optimization Manual on Silvermont INC or DEC instructions require an additional uop to merge the flags. As a result, a branch instruction depending on an INC or a DEC instruction incurs a 1 cycle penalty. Differential Revision: http://reviews.llvm.org/D3990 llvm-svn: 210466
* [AArch64] Missing aliases for CMP/CMN [W]SP with no shiftArtyom Skrobov2014-06-091-0/+4
| | | | llvm-svn: 210464
* [mips][mips64r6] Add LDPC instructionZoran Jovanovic2014-06-098-6/+62
| | | | | | Differential Revision: http://reviews.llvm.org/D3822 llvm-svn: 210460
* [AArch64] Fix the ordering of the accumulate operand in SchedRW list.Chad Rosier2014-06-091-3/+3
| | | | | | | Patch by Dave Estes <cestes@codeaurora.org> http://reviews.llvm.org/D4037 llvm-svn: 210446
* [AArch64] When combining constant mul of power of 2 plus/minus 1, prefer shiftChad Rosier2014-06-091-9/+9
| | | | | | | plus add. The shift can be folded into the add. This only effects codegen when the constant is 3. llvm-svn: 210445
* [C++11] Use 'nullptr'.Craig Topper2014-06-083-3/+3
| | | | llvm-svn: 210442
* X86: simplify data layout calculationSaleem Abdulrasool2014-06-081-3/+2
| | | | | | | | X86Subtarget::isTargetCygMing || X86Subtarget::isTargetKnownWindowsMSVC is equivalent to all Windows environments. Simplify the check to isOSWindows. NFC. llvm-svn: 210431
* AsmMatchers: Use unique_ptr to manage ownership of MCParsedAsmOperandDavid Blaikie2014-06-0810-1067/+936
| | | | | | | | | | | | I saw at least a memory leak or two from inspection (on probably untested error paths) and r206991, which was the original inspiration for this change. I ran this idea by Jim Grosbach a few weeks ago & he was OK with it. Since it's a basically mechanical patch that seemed sufficient - usual post-commit review, revert, etc, as needed. llvm-svn: 210427
* Revert "Do materialize for floating point"Alp Toker2014-06-081-23/+2
| | | | | | | | | | | | | | | | | | | | | | | 1) The commit was made despite profound lack of understanding: "I did not understand the comment about using dyn_cast instead of isa. I will commit as is and make the update after. You can explain what you meant to me." Commit first, understand later isn't OK. 2) Review comments were simply ignored: "Can you edit the summary to describe what the patch is for? It appears to be a list of commits at the moment." 3) The patch got LGTM'd off-list without any indication of readiness. 4) The public mailing list was excluded from patch review so all of this was hidden from the community. This reverts commit r210414. llvm-svn: 210424
* Remove outdated CMake MSVC workaroundAlp Toker2014-06-081-7/+1
| | | | llvm-svn: 210421
* Do materialize for floating pointReed Kotler2014-06-081-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: start to do simple constants finish simplestore add test case format Merge branch 'master' into 1756_8 Add basic functionality for assignment of ints. This creates a lot of core infrastructure in which to add, with little effort, quite a bit more to mips fast-isel Merge branch 'master' into 1756_8 Add basic functionality for assignment of ints. This creates a lot of core infrastructure in which to add, with little effort, quite a bit more to mips fast-isel in progress finish integer materialize test cases test cases in progress Finish up fast-isel materialize for ints. Finish materialize for ints test cases simplestorei.ll Merge branch 'master' into 1756_8 fix fp constants for fast-isel Merge branch '1758_1' of dmz-portal.mips.com:llvm into 1758_1 in progress lastest for fp materialization clean up Merge branch 'master' into 1758_1 formatting add test case finish test case Merge branch 'master' into 1758_2 Test Plan: simplestore.ll simplestore.ll Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3659 llvm-svn: 210414
* start to clean up buildMI calls in mips fast-iselReed Kotler2014-06-081-26/+24
| | | | | | | | | | | | | | | | | Summary: Merge branch 'master' into 1758_6 Test Plan: No functionality change. Run "make check" and run test-suite. Because our servers are not yet running again I have not yet run test-suite. I will further review myself before submission. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3819 llvm-svn: 210413
* include MipsGenFastISel.incReed Kotler2014-06-081-5/+17
| | | | | | | | | | | | | | | | | | Summary: Included this file which is needed to enable tablegen generated functionality for fast mips-isel Test Plan: This has no visible functionality by itself but just adding the include file creates some issues so I have it as a separate patch. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3812 llvm-svn: 210410
* Fix typosAlp Toker2014-06-071-1/+1
| | | | llvm-svn: 210401
* ARM: correct assertion for long-calls on WoASaleem Abdulrasool2014-06-071-2/+3
| | | | | | | | | | | COFF/PE, so the relocation model is never static. Loosen the assertion accordingly. The relocation can still be emitted properly, as it will be converted to an IMAGE_REL_ARM_ADDR32 which will be resolved by the loader taking the base relocation into account. This is necessary to permit the emission of long calls which can be controlled via the -mlong-calls option in the driver. llvm-svn: 210399
* Replace the use of TargetMachine with a tiny bool variable.Eric Christopher2014-06-063-8/+6
| | | | llvm-svn: 210386
* Remove all local variables from X86SelectionDAGInfo, the DAG hasEric Christopher2014-06-063-35/+29
| | | | | | all of the ones we were stashing away on startup. llvm-svn: 210385
* X86: Don't turn shifts into ands if there's another use that may not check ↵Benjamin Kramer2014-06-061-1/+1
| | | | | | | | for equality. Fixes PR19964. llvm-svn: 210371
* Have TargetSelectionDAGInfo take a DataLayout initializer rather thanEric Christopher2014-06-0611-19/+13
| | | | | | a TargetMachine since the only thing it wants is DataLayout. llvm-svn: 210366
* Fixed a bug in lowering shuffle_vectors to insertpsFilipe Cabecinhas2014-06-061-9/+20
| | | | | | | | | | | | | | Summary: We were being too strict and not accounting for undefs. Added a test case and fixed another one where we improved codegen. Reviewers: grosbach, nadav, delena Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D4039 llvm-svn: 210361
* [PPC64LE] Fix lowering of BUILD_VECTOR and SHUFFLE_VECTOR for little endianBill Schmidt2014-06-061-3/+34
| | | | | | | | | | | | | | | This patch fixes a couple of lowering issues for little endian PowerPC. The code for lowering BUILD_VECTOR contains a number of optimizations that are only valid for big endian. For now, we disable those optimizations for correctness. In the future, we will add analogous optimizations that are correct for little endian. When lowering a SHUFFLE_VECTOR to a VPERM operation, we again need to make the now-familiar transformation of swapping the input operands and complementing the permute control vector. Correctness of this transformation is tested by the accompanying test case. llvm-svn: 210336
* Remove X86Subtarget from the X86FrameLowering constructor sinceEric Christopher2014-06-052-15/+11
| | | | | | | we can just pass in the values we already know and we're not caching the subtarget anymore. llvm-svn: 210292
* Remove caching of the subtarget for X86FrameLowering.Eric Christopher2014-06-052-6/+9
| | | | llvm-svn: 210290
* Remove duplicate copy of InstrItineraryData from the TargetMachine,Eric Christopher2014-06-052-3/+1
| | | | | | it's already on the subtarget. llvm-svn: 210289
* Add a new attribute called 'jumptable' that creates jump-instruction tables ↵Tom Roeder2014-06-054-0/+48
| | | | | | | | | | | | for functions marked with this attribute. It includes a pass that rewrites all indirect calls to jumptable functions to pass through these tables. This also adds backend support for generating the jump-instruction tables on ARM and X86. Note that since the jumptable attribute creates a second function pointer for a function, any function marked with jumptable must also be marked with unnamed_addr. llvm-svn: 210280
* [PPC64LE] Temporarily disable VSX support in little-endian modeBill Schmidt2014-06-051-0/+5
| | | | | | | | | | This is a preliminary patch for the PowerPC64LE support. In stage 1 of the vector support, we will support the VMX (Altivec) instruction set, but will not yet support the VSX instructions. This is merely a staging issue to provide functional vector support as soon as possible. llvm-svn: 210271
* [SystemZ] Do not install IfConverter pass at -O0Ulrich Weigand2014-06-051-1/+2
| | | | | | | | When not optimizing, do not run the IfConverter pass, this makes debugging more difficult (and causes a testsuite failure in DebugInfo/unconditional-branch.ll). llvm-svn: 210263
* [mips] Modify long branch for NaCl:Sasa Stankovic2014-06-051-6/+30
| | | | | | | | | * Move the instruction that changes sp outside of the branch delay slot. * Bundle-align the target of indirect branch. Differential Revision: http://llvm-reviews.chandlerc.com/D3928 llvm-svn: 210262
* We've got a getSlotSize call already that we use everywhere else,Eric Christopher2014-06-051-2/+3
| | | | | | use it here too. llvm-svn: 210227
* R600/SI: Match rsq instructionsMatt Arsenault2014-06-051-2/+6
| | | | llvm-svn: 210226
* 80-columns.Eric Christopher2014-06-051-1/+2
| | | | llvm-svn: 210224
* Remove uses of the TargetMachine from X86FrameLowering.Eric Christopher2014-06-053-19/+25
| | | | llvm-svn: 210223
* Use nullptrMatt Arsenault2014-06-051-3/+2
| | | | llvm-svn: 210222
* Two small enhancements for the JIT.Yaron Keren2014-06-041-1/+6
| | | | | | | | | | When JITting a large project such as Boost it's quite hard to figure out the problematic inline asm without debug location. This patch provides debug location printout before the JIT aborts due to inline asm. printDebugLoc() was exposed from MachineInstr.cpp and reused here. If the JIT run with debug info, don't bomb on DBG_VALUE but ignore them. http://reviews.llvm.org/D3416 llvm-svn: 210201
* [AArch64] clang-format the load/store optimizer.Tilmann Scheller2014-06-041-16/+25
| | | | | | No change in functionality. llvm-svn: 210182
* [AArch64] Fix some LLVM Coding Standards violations in the load/store optimizer.Tilmann Scheller2014-06-041-19/+19
| | | | | | | | Variable names should start with an upper case letter. No change in functionality. llvm-svn: 210181
* Fix a use of uninitialized value. OldCC is set when IsCmpZero || IsSwapped ↵Nick Lewycky2014-06-041-1/+1
| | | | | | and read when ShouldUpdateCC || IsSwapped, and ShouldUpdateCC is independent. Fixes PR19932, but no test since I wasn't able to get any symptoms to appear, not even with valgrind and the testcase from the PR. It's clear what happened from inspection of the code. llvm-svn: 210168
* Add a subtarget hook: enablePostMachineScheduler.Andrew Trick2014-06-043-0/+14
| | | | | | | | | | | | | | | As requested by AArch64 subtargets. Note that this will have no effect until the AArch64 target actually enables the pass like this: substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); As soon as armv7 switches over, PostMachineScheduler will become the default postRA scheduler, so this won't be necessary any more. Targets using the old postRA schedule would then do: substitutePass(&PostMachineSchedulerID, &PostRASchedulerID); llvm-svn: 210167
* Fix typosMatt Arsenault2014-06-032-8/+8
| | | | llvm-svn: 210135
* Revert r209381 as it isn't a local variable. Add a testcase so thatEric Christopher2014-06-031-0/+1
| | | | | | we know next time this happens. llvm-svn: 210127
* Fixup formatting in the pass.Eric Christopher2014-06-031-86/+86
| | | | llvm-svn: 210126
* [AArch64] Fix typo in load/store optimizer.Tilmann Scheller2014-06-031-1/+1
| | | | llvm-svn: 210114
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