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* [AVX512] Remove masked store intrinsics. Clang now emits generic masked ↵Craig Topper2016-05-311-30/+0
| | | | | | | | store intrinsics instead. The intrinsics will be autoupgraded to the same generic masked stores. llvm-svn: 271245
* X86: permit using SjLj EH on x86 targets as an optionSaleem Abdulrasool2016-05-313-1/+277
| | | | | | | | | | | This adds support to the backed to actually support SjLj EH as an exception model. This is *NOT* the default model, and requires explicitly opting into it from the frontend. GCC supports this model and for MinGW can still be enabled via the `--using-sjlj-exceptions` options. Addresses PR27749! llvm-svn: 271244
* [X86] Remove SSE/AVX unaligned store intrinsics as clang no longer uses ↵Craig Topper2016-05-301-29/+0
| | | | | | them. Auto upgrade to native unaligned store instructions. llvm-svn: 271236
* Fix a crash when producing COFF.Rafael Espindola2016-05-301-0/+2
| | | | llvm-svn: 271229
* [BPF] Remove exit-on-error from tests (PR27768, PR27769)Diana Picus2016-05-301-1/+5
| | | | | | | | | | | The exit-on-error flag is necessary to avoid some assertions/unreachables. We can get past them by creating a few dummy nodes. Fixes PR27768, PR27769. Differential Revision: http://reviews.llvm.org/D20726 llvm-svn: 271200
* Move RelaxELFRel out to llvm-mc.Rafael Espindola2016-05-291-6/+0
| | | | llvm-svn: 271160
* [X86][SSE] (Reapplied) Replace (V)PMOVSX and (V)PMOVZX integer extension ↵Simon Pilgrim2016-05-281-18/+0
| | | | | | | | | | | | intrinsics with generic IR (llvm) This patch removes the llvm intrinsics VPMOVSX and (V)PMOVZX sign/zero extension intrinsics and auto-upgrades to SEXT/ZEXT calls instead. We already did this for SSE41 PMOVSX sometime ago so much of that implementation can be reused. Reapplied now that the the companion patch (D20684) removes/auto-upgrade the clang intrinsics has been committed. Differential Revision: http://reviews.llvm.org/D20686 llvm-svn: 271131
* Fix production of R_X86_64_GOTPCRELX/R_X86_64_REX_GOTPCRELX.Rafael Espindola2016-05-285-31/+70
| | | | | | | | We were producing R_X86_64_GOTPCRELX for invalid instructions and sometimes producing R_X86_64_GOTPCRELX instead of R_X86_64_REX_GOTPCRELX. llvm-svn: 271118
* [x86] avoid printing unnecessary sign bits of hex immediates in asm comments ↵Sanjay Patel2016-05-281-4/+13
| | | | | | | | | | | (PR20347) It would be better to check the valid/expected size of the immediate operand, but this is generally better than what we print right now. Differential Revision: http://reviews.llvm.org/D20385 llvm-svn: 271114
* [X86] Try to zero elts when lowering 256-bit shuffle with PSHUFB.Ahmed Bougacha2016-05-281-35/+66
| | | | | | | | Otherwise we fallback to a blend of PSHUFBs later on. Differential Revision: http://reviews.llvm.org/D19661 llvm-svn: 271113
* Simplify and clang-format a table.Rafael Espindola2016-05-281-5/+5
| | | | llvm-svn: 271112
* Fix default reloc model on ARM.Rafael Espindola2016-05-281-2/+2
| | | | llvm-svn: 271111
* Revert "Revert "Map DynamicNoPIC to Static on non-darwin.""Renato Golin2016-05-281-0/+5
| | | | | | | | This reverts commit r271096, as reverting it broke even more buildbots! But that also means I'll break on ARM again... :( llvm-svn: 271099
* Revert "Map DynamicNoPIC to Static on non-darwin."Renato Golin2016-05-281-5/+0
| | | | | | This reverts commit r271052, as it broke some ARM buildbots. llvm-svn: 271096
* [Hexagon] Add option to enable subregister liveness trackingKrzysztof Parzyszek2016-05-282-0/+11
| | | | llvm-svn: 271088
* [Hexagon] Separate C8 and USR to avoid unwanted subregister compositionKrzysztof Parzyszek2016-05-282-6/+18
| | | | | | | | Composing subreg_loreg with subreg_oveflow leads to strange results with lane masks for register classes with subreg_loreg. In particular, dead lane detection generates incorrect code. llvm-svn: 271087
* AArch64: Fix indentationMatthias Braun2016-05-281-9/+9
| | | | llvm-svn: 271084
* AMDGPU: Fix trailing whitespaceMatt Arsenault2016-05-281-5/+5
| | | | llvm-svn: 271081
* AMDGPU: Add fract intrinsicMatt Arsenault2016-05-283-36/+21
| | | | | | | | | Remove broken patterns matching it. This was matching the unsafe math pattern and expanding the fix for the buggy instruction from the pattern. The problems are also on CI. Remove the workarounds and only use fract with unsafe math or from the intrinsic. llvm-svn: 271078
* Start using shouldAssumeDSOLocal on ARM.Rafael Espindola2016-05-271-29/+9
| | | | | | Given where this is used it should be a nop. llvm-svn: 271066
* AArch64Subtarget: Use default member initializersMatthias Braun2016-05-272-19/+15
| | | | llvm-svn: 271057
* Map DynamicNoPIC to Static on non-darwin.Rafael Espindola2016-05-271-0/+5
| | | | | | | DynamicNoPIC was only every used on darwin. This maps it to static on ELF. It matches what is done on X86. llvm-svn: 271052
* [Hexagon] Use standard macros to initialize HexagonExpandCondsets passKrzysztof Parzyszek2016-05-271-12/+7
| | | | llvm-svn: 271045
* [Hexagon] Do not create passes in the constructor of HexagonPassConfigKrzysztof Parzyszek2016-05-271-9/+5
| | | | | | | When running mir tests, a pass created in that constructor would not be freed, leading to memory leaks. llvm-svn: 271043
* [X86] Detect SAD patterns and emit psadbw instructions.Michael Kuperstein2016-05-271-0/+140
| | | | | | | | This recommits r267649 with a fix for PR27539. Differential Revision: http://reviews.llvm.org/D20598 llvm-svn: 271033
* [X86] Clarify PSHUFB+blend lowering function name. NFC.Ahmed Bougacha2016-05-271-9/+11
| | | | | | Also guard against v32i8 users. llvm-svn: 271024
* [ARM] Remove tBLXr Pat made redundant by r269101. NFCI.Ahmed Bougacha2016-05-272-10/+0
| | | | llvm-svn: 271023
* Use StringRef::startswith instead of find(...) == 0.Benjamin Kramer2016-05-271-1/+1
| | | | | | It's faster and easier to read. llvm-svn: 271018
* [sparc] Simplify a slow and verbose way of checking if a string starts with ↵Benjamin Kramer2016-05-271-6/+4
| | | | | | | | "ld". PR27904. llvm-svn: 271016
* Apply clang-tidy's misc-move-constructor-init throughout LLVM.Benjamin Kramer2016-05-272-3/+5
| | | | | | No functionality change intended, maybe a tiny performance improvement. llvm-svn: 270997
* [mips] Weaken asm predicate for memory offsetsSimon Dardis2016-05-271-3/+7
| | | | | | | | | | | | The isMemWithSimmOffset predicate rejects relocations which is incorrect behaviour. Linkers and other tools should handle|warn|error when the field overflows. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D20727 llvm-svn: 270995
* [AMDGPU][llvm-mc] Square-braced-syntax for registers - make ":expr2" optional.Artem Tamazov2016-05-271-6/+10
| | | | | | | | | | | | | | | | | Register numbers may be specified as assembly-time expressions. This feature can be useful in macros and alike. However, expressions are supported within sqare braces only. Sqare braces were initially intended to support specifying of multiple (pairs/quads...) registers. Syntax like v[8:8] which specifies single register is also supported. That allows expressions but looks a bit unnatural. This change supports syntax REG[EXPR]. Tests added. Differential Revision: http://reviews.llvm.org/D20588 llvm-svn: 270990
* Avoid some copies by using const references.Benjamin Kramer2016-05-276-8/+5
| | | | | | | clang-tidy's performance-unnecessary-copy-initialization with some manual fixes. No functional changes intended. llvm-svn: 270988
* Apply clang-tidy's misc-static-assert where it makes sense.Benjamin Kramer2016-05-277-29/+26
| | | | | | | Also fold conditions into assert(0) where it makes sense. No functional change intended. llvm-svn: 270982
* [sparc] Remove some unused (and undefined) declarations.Benjamin Kramer2016-05-274-14/+2
| | | | | | No functionality change. llvm-svn: 270981
* [hexagon] Move BlockRanges and RDF stuff into the llvm namespace.Benjamin Kramer2016-05-2710-28/+28
| | | | | | No functional change intended. llvm-svn: 270980
* [sparc] Move LEON passes into llvm namespace.Benjamin Kramer2016-05-272-4/+6
| | | | | | Also give them library visiblity while there. llvm-svn: 270979
* Revert: r270973 - [X86][SSE] Replace (V)PMOVSX and (V)PMOVZX integer ↵Simon Pilgrim2016-05-271-0/+18
| | | | | | extension intrinsics with generic IR (llvm) llvm-svn: 270976
* [X86][SSE] Replace (V)PMOVSX and (V)PMOVZX integer extension intrinsics with ↵Simon Pilgrim2016-05-271-18/+0
| | | | | | | | | | | | generic IR (llvm) This patch removes the llvm intrinsics VPMOVSX and (V)PMOVZX sign/zero extension intrinsics and auto-upgrades to SEXT/ZEXT calls instead. We already did this for SSE41 PMOVSX sometime ago so much of that implementation can be reused. A companion patch (D20684) removes/auto-upgrade the clang intrinsics. Differential Revision: http://reviews.llvm.org/D20686 llvm-svn: 270973
* [Hexagon] Enable the post-RA schedulerKrzysztof Parzyszek2016-05-263-7/+91
| | | | | | | | | The aggressive anti-dependency breaker can rename the restored callee- saved registers. To prevent this, mark these registers are live on all paths to the return/tail-call instructions, and add implicit use operands for them to these instructions. llvm-svn: 270898
* [AArch64] Generate rev16/rev32 from bswap + srl when upper bits are known zero.Chad Rosier2016-05-261-1/+31
| | | | | | | | | | | | | | | | | Canonicalize (srl (bswap i32 x), 16) to (rotr (bswap i32 x), 16), if the high 16-bits of x are zero. Similarly, canonicalize (srl (bswap i64 x), 32) to (rotr (bswap i64 x), 32), if the high 32-bits of x are zero. test_rev_w_srl16: test_rev_w_srl16: and w8, w0, #0xffff and w8, w0, #0xffff rev w8, w8 ---> rev16 w0, w8 lsr w0, w8, #16 test_rev_x_srl32: test_rev_x_srl32: rev x8, x8 ---> rev32 x0, x8 lsr x0, x8, #32 llvm-svn: 270896
* AMDGPU/SI: Enable load-store-opt by default.Changpeng Fang2016-05-261-1/+1
| | | | | | | | | | Summary: Enable load-store-opt by default, and update LIT tests. Reviewers: arsenm Differential Revision: http://reviews.llvm.org/D20694 llvm-svn: 270894
* Init member structs in constructor.Artem Belevich2016-05-261-3/+9
| | | | | | | Fixes build error on windows where MSVC does not support list initialization inside member initializer list. llvm-svn: 270877
* [NVPTX] Added NVVMIntrRange passArtem Belevich2016-05-264-0/+159
| | | | | | | | | | | | NVVMIntrRange adds !range metadata to calls of NVVM intrinsics that return values within known limited range. This allows LLVM to generate optimal code for indexing arrays based on tid/ctaid which is a frequently used pattern in CUDA code. Differential Revision: http://reviews.llvm.org/D20644 llvm-svn: 270872
* [AMDGPU][llvm-mc] s_getreg/setreg* - hwreg - factor out strings/literals etc.Artem Tamazov2016-05-269-159/+196
| | | | | | | | | | | Hwreg(...) syntax implementation unified with sendmsg(...). Common strings moved to Utils MathExtras.h functionality utilized. Added missing build dependency in Disassembler. Differential Revision: http://reviews.llvm.org/D20381 llvm-svn: 270871
* Fix build warning introduced in r270552 "[AMDGPU][llvm-mc] Disassembler: ↵Artem Tamazov2016-05-261-1/+2
| | | | | | support for TTMP/TBA/TMA registers." llvm-svn: 270859
* [X86][SSE] When lowering a 256-bit shuffle as PMOVZX, reduce the input ↵Simon Pilgrim2016-05-261-1/+7
| | | | | | | | vector to the lower 128-bit subvector. Most often as not this is what it started out as, the extraction is zero-cost on AVX and the PMOVZX/PMOVSX folding logic is based around 128-bit loads. llvm-svn: 270858
* [Hexagon] Select the aggressive anti-dependency breakerKrzysztof Parzyszek2016-05-261-0/+2
| | | | llvm-svn: 270857
* [AMDGPU] Remove exit-on-error flag from test (PR27762)Diana Picus2016-05-261-1/+1
| | | | | | | | | | Similar to r269948, but for argument lowering. Fixes PR27762 Differential Revision: http://reviews.llvm.org/D20430 llvm-svn: 270856
* [BPF] Remove exit-on-error flag in test (PR27767)Diana Picus2016-05-261-0/+1
| | | | | | | | | | | | The exit-on-error flag is needed to avoid an assert where llvm::SelectionDAGISel::LowerArguments doesn't create enough arguments. Fill up with zeroes to reach the right number of args. Fixes PR27767. Differential Revision: http://reviews.llvm.org/D20571 llvm-svn: 270855
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