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* Appease GCC's -Wparentheses.Matt Beaumont-Gay2012-12-041-2/+2
| | | | | | (TIL that Clang's -Wparentheses ignores 'x || y && "foo"' on purpose. Neat.) llvm-svn: 169337
* ARM custom lower ctpop for vector types. Patch by Pete Couperus.Evan Cheng2012-12-041-0/+117
| | | | llvm-svn: 169325
* Define store instructions with base+register offset addressing modeJyotsna Verma2012-12-041-352/+116
| | | | | | using multiclass. llvm-svn: 169314
* Make NaCl naming consistent. The triple OSType is called NaCl and is representedEli Bendersky2012-12-042-2/+2
| | | | | | | | | textually as NativeClient. Also added a link to the native client project for readers unfamiliar with it. A Clang patch will follow shortly. llvm-svn: 169291
* Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count ↵Jyotsna Verma2012-12-043-17/+97
| | | | | | | | trailing/leading zeros) instructions. llvm-svn: 169287
* Add constant extender support to ALU32 instructions for V2.Jyotsna Verma2012-12-041-51/+79
| | | | llvm-svn: 169284
* This patch introduces initial-exec model support for thread-local storageBill Schmidt2012-12-0413-15/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on 64-bit PowerPC ELF. The patch includes code to handle external assembly and MC output with the integrated assembler. It intentionally does not support the "old" JIT. For the initial-exec TLS model, the ABI requires the following to calculate the address of external thread-local variable x: Code sequence Relocation Symbol ld 9,x@got@tprel(2) R_PPC64_GOT_TPREL16_DS x add 9,9,x@tls R_PPC64_TLS x The register 9 is arbitrary here. The linker will replace x@got@tprel with the offset relative to the thread pointer to the generated GOT entry for symbol x. It will replace x@tls with the thread-pointer register (13). The two test cases verify correct assembly output and relocation output as just described. PowerPC-specific selection node variants are added for the two instructions above: LD_GOT_TPREL and ADD_TLS. These are inserted when an initial-exec global variable is encountered by PPCTargetLowering::LowerGlobalTLSAddress(), and later lowered to machine instructions LDgotTPREL and ADD8TLS. LDgotTPREL is a pseudo that uses the same LDrs support added for medium code model's LDtocL, with a different relocation type. The rest of the processing is straightforward. llvm-svn: 169281
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-0449-100/+100
| | | | | | | | | | missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
* Move all operand definitions into HexagonOperands.tdJyotsna Verma2012-12-042-53/+57
| | | | llvm-svn: 169213
* Move generic Hexagon subtarget information into Hexagon.tdJyotsna Verma2012-12-042-64/+101
| | | | llvm-svn: 169212
* Remove the old TRI::ResolveRegAllocHint() and getRawAllocationOrder() hooks.Jakob Stoklund Olesen2012-12-042-270/+0
| | | | | | | These functions have been replaced by TRI::getRegAllocationHints() which provides the same capabilities. llvm-svn: 169192
* Classic JIT is still being supported by MIPS, along with MCJIT.Akira Hatanaka2012-12-033-11/+24
| | | | | | | | | This change adds endian-awareness to MipsJITInfo and emitWordLE in MipsCodeEmitter has become emitWord now to support both endianness. Patch by Petar Jovanovic. llvm-svn: 169177
* Functions in MipsCodeEmitter.cpp that expand unaligned loads/stores are deadAkira Hatanaka2012-12-031-103/+0
| | | | | | | | code. Removing it. Patch by Petar Jovanovic. llvm-svn: 169174
* Implement ARMBaseRegisterInfo::getRegAllocationHints().Jakob Stoklund Olesen2012-12-032-0/+65
| | | | | | | This provides the same functionality as getRawAllocationOrder() for the even/odd hints, but without the many constant register arrays. llvm-svn: 169169
* Define store instructions with base+immediate offset addressing modeJyotsna Verma2012-12-032-185/+78
| | | | | | using multiclass. llvm-svn: 169168
* Define load instructions with base+immediate offset addressing modeJyotsna Verma2012-12-031-203/+73
| | | | | | using multiclass. llvm-svn: 169153
* Define unsigned const-ext predicates.Jyotsna Verma2012-12-031-0/+128
| | | | llvm-svn: 169149
* Removing unnecessary 'else' statement from the predicates defined in ↵Jyotsna Verma2012-12-031-48/+12
| | | | | | HexagonOperards.td. llvm-svn: 169148
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-03181-798/+793
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Define signed const-ext predicates.Jyotsna Verma2012-12-031-0/+131
| | | | llvm-svn: 169117
* Codegen failure for vmull with small vectorsSebastian Pop2012-11-301-13/+74
| | | | | | | | | | | | | | | | | | | | | | | | | Codegen was failing with an assertion because of unexpected vector operands when legalizing the selection DAG for a MUL instruction. The asserting code was legalizing multiplies for vectors of size 128 bits. It uses a custom lowering to try and detect cases where it can use a VMULL instruction instead of a VMOVL + VMUL. The code was looking for input operands to the MUL that had been sign or zero extended. If it found the extended operands it would drop the sign/zero extension and use the original vector size as input to a VMULL instruction. The code assumed that the original input vector was 64 bits so that after dropping the extension it would fit directly into a D register and could be used as an operand of a VMULL instruction. The input code that trigger the failure used a vector of <4 x i8> that was sign extended to <4 x i32>. It was not safe to drop the sign extension in this case because the original vector is only 32 bits wide. The fix is to insert a sign extension for the vector to reach the required 64 bit size. In this particular example, the vector would need to be sign extented to a <4 x i16>. llvm-svn: 169024
* Use multiclass for the load instructions with MEMri operand.Jyotsna Verma2012-11-301-184/+66
| | | | llvm-svn: 169018
* This patch fixes the Altivec addend construction for the fused multiply-addAdhemerval Zanella2012-11-301-5/+7
| | | | | | | | | | | | | | | instruction (vmaddfp) to conform with IEEE to ensure the sign of a zero result when resulting product is -0.0. The -0.0 vector addend to vmaddfp is generated by a creating a vector with full bits sets and then shifting each elements by 31-bits to the left, resulting in a vector of 0x80000000 (or -0.0 as float). The 'buildvec_canonicalize.ll' was adjusted to reflect this change and the 'vec_mul.ll' was complemented with the float vector multiplication test. llvm-svn: 168998
* Switch LLVM_USE_RVALUE_REFERENCES to LLVM_HAS_RVALUE_REFERENCES.Chandler Carruth2012-11-301-1/+1
| | | | | | | | | | | | | | Rationale: 1) This was the name in the comment block. ;] 2) It matches Clang's __has_feature naming convention. 3) It matches other compiler-feature-test conventions. Sorry for the noise. =] I've also switch the comment block to use a \brief tag and not duplicate the name. llvm-svn: 168996
* Use multiclass for the store instructions with MEMri operand.Jyotsna Verma2012-11-302-163/+64
| | | | llvm-svn: 168983
* Use multiclass for the load instructions with 'base + register offset'Jyotsna Verma2012-11-301-277/+97
| | | | | | addressing mode. llvm-svn: 168976
* Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInstKevin Enderby2012-11-291-1/+7
| | | | | | which would then cause an assert when printed. rdar://11437956 llvm-svn: 168960
* Add cortex-a5 subtarget to the supported ARM architecturesQuentin Colombet2012-11-292-1/+12
| | | | llvm-svn: 168933
* rdar://12100355 (part 1)Shuxin Yang2012-11-293-1/+20
| | | | | | | | | | | | | | This revision attempts to recognize following population-count pattern: while(a) { c++; ... ; a &= a - 1; ... }, where <c> and <a>could be used multiple times in the loop body. TODO: On X8664 and ARM, __buildin_ctpop() are not expanded to a efficent instruction sequence, which need to be improved in the following commits. Reviewed by Nadav, really appreciate! llvm-svn: 168931
* Use multiclass for 'transfer' instructions.Jyotsna Verma2012-11-292-80/+98
| | | | llvm-svn: 168929
* Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend.Silviu Baranga2012-11-294-12/+102
| | | | llvm-svn: 168886
* Allow targets to prefer TypeSplitVector over TypePromoteInteger when ↵Justin Holewinski2012-11-292-0/+7
| | | | | | | | computing the legalization method for vectors For some targets, it is desirable to prefer scalarizing <N x i1> instead of promoting to a larger legal type, such as <N x i32>. llvm-svn: 168882
* I changed hasAVX() to hasFp256() and hasAVX2() to hasInt256() in ↵Elena Demikhovsky2012-11-292-102/+104
| | | | | | | | X86IselLowering.cpp. The logic was not changed, only names. llvm-svn: 168875
* Define signed const-ext immediate operands and their predicates.Jyotsna Verma2012-11-282-0/+122
| | | | llvm-svn: 168810
* ARM: Implement CanLowerReturn so large vectors get expanded into sret.Benjamin Kramer2012-11-282-0/+17
| | | | | | Fixes 14337. llvm-svn: 168809
* Fix initial frame state on powerpc64.Ulrich Weigand2012-11-281-1/+1
| | | | | | | | | The createPPCMCAsmInfo routine used PPC::R1 as the initial frame pointer register, but on PPC64 the 32-bit R1 register does not have a corresponding DWARF number, causing invalid CIE initial frame state to be emitted. Fix by using PPC::X1 instead. llvm-svn: 168799
* Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen2012-11-284-12/+12
| | | | | | This class has been merged into its super-class TargetInstrInfo. llvm-svn: 168760
* Move Target{Instr,Register}Info.cpp into lib/CodeGen.Jakob Stoklund Olesen2012-11-283-338/+0
| | | | | | | | | | | | | | | | The Target library is not allowed to depend on the large CodeGen library, but the TRI and TII classes provide abstract interfaces that require both caller and callee to link to CodeGen. The implementation files for these classes provide default implementations of some of the hooks. These methods may need to reference CodeGen, so they belong in that library. We already have a number of methods implemented in the TargetInstrInfoImpl sub-class because of that. I will merge that class into the parent next. llvm-svn: 168758
* This patch makes medium code model the default for 64-bit PowerPC ELF.Bill Schmidt2012-11-271-0/+5
| | | | | | | | | When the CodeGenInfo is to be created for the PPC64 target machine, a default code-model selection is converted to CodeModel::Medium provided we are not targeting the Darwin OS. Defaults for Darwin are unaffected. llvm-svn: 168747
* [arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier2012-11-271-9/+7
| | | | | | | | | classes. The vast majority of the remaining issues are due to uses of invalid registers, which are defined by getRegForValue(). Those will be a little more challenging to cleanup. rdar://12719844 llvm-svn: 168735
* [arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier2012-11-271-2/+4
| | | | | | | classes. rdar://12719844 llvm-svn: 168733
* [arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier2012-11-271-5/+6
| | | | | | | classes. Also a bit of cleanup. rdar://12719844 llvm-svn: 168728
* X86: do not fold load instructions such as [V]MOVS[S|D] to other instructionsManman Ren2012-11-271-0/+15
| | | | | | | | | | | when the destination register is wider than the memory load. These load instructions load from m32 or m64 and set the upper bits to zero, while the folded instructions may accept m128. rdar://12721174 llvm-svn: 168710
* This patch implements medium code model support for 64-bit PowerPC.Bill Schmidt2012-11-277-10/+233
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default for 64-bit PowerPC is small code model, in which TOC entries must be addressable using a 16-bit offset from the TOC pointer. Additionally, only TOC entries are addressed via the TOC pointer. With medium code model, TOC entries and data sections can all be addressed via the TOC pointer using a 32-bit offset. Cooperation with the linker allows 16-bit offsets to be used when these are sufficient, reducing the number of extra instructions that need to be executed. Medium code model also does not generate explicit TOC entries in ".section toc" for variables that are wholly internal to the compilation unit. Consider a load of an external 4-byte integer. With small code model, the compiler generates: ld 3, .LC1@toc(2) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc ei[TC],ei With medium model, it instead generates: addis 3, 2, .LC1@toc@ha ld 3, .LC1@toc@l(3) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc ei[TC],ei Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the 32-bit offset of ei's TOC entry from the TOC base pointer. Similarly, .LC1@toc@l is a relocation requesting the lower 16 bits. Note that if the linker determines that ei's TOC entry is within a 16-bit offset of the TOC base pointer, it will replace the "addis" with a "nop", and replace the "ld" with the identical "ld" instruction from the small code model example. Consider next a load of a function-scope static integer. For small code model, the compiler generates: ld 3, .LC1@toc(2) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc test_fn_static.si[TC],test_fn_static.si .type test_fn_static.si,@object .local test_fn_static.si .comm test_fn_static.si,4,4 For medium code model, the compiler generates: addis 3, 2, test_fn_static.si@toc@ha addi 3, 3, test_fn_static.si@toc@l lwz 4, 0(3) .type test_fn_static.si,@object .local test_fn_static.si .comm test_fn_static.si,4,4 Again, the linker may replace the "addis" with a "nop", calculating only a 16-bit offset when this is sufficient. Note that it would be more efficient for the compiler to generate: addis 3, 2, test_fn_static.si@toc@ha lwz 4, test_fn_static.si@toc@l(3) The current patch does not perform this optimization yet. This will be addressed as a peephole optimization in a later patch. For the moment, the default code model for 64-bit PowerPC will remain the small code model. We plan to eventually change the default to medium code model, which matches current upstream GCC behavior. Note that the different code models are ABI-compatible, so code compiled with different models will be linked and execute correctly. I've tested the regression suite and the application/benchmark test suite in two ways: Once with the patch as submitted here, and once with additional logic to force medium code model as the default. The tests all compile cleanly, with one exception. The mandel-2 application test fails due to an unrelated ABI compatibility with passing complex numbers. It just so happens that small code model was incredibly lucky, in that temporary values in floating-point registers held the expected values needed by the external library routine that was called incorrectly. My current thought is to correct the ABI problems with _Complex before making medium code model the default, to avoid introducing this "regression." Here are a few comments on how the patch works, since the selection code can be difficult to follow: The existing logic for small code model defines three pseudo-instructions: LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for constant pool addresses. These are expanded by SelectCodeCommon(). The pseudo-instruction approach doesn't work for medium code model, because we need to generate two instructions when we match the same pattern. Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY node for medium code model, and generates an ADDIStocHA followed by either a LDtocL or an ADDItocL. These new node types correspond naturally to the sequences described above. The addis/ld sequence is generated for the following cases: * Jump table addresses * Function addresses * External global variables * Tentative definitions of global variables (common linkage) The addis/addi sequence is generated for the following cases: * Constant pool entries * File-scope static global variables * Function-scope static variables Expanding to the two-instruction sequences at select time exposes the instructions to subsequent optimization, particularly scheduling. The rest of the processing occurs at assembly time, in PPCAsmPrinter::EmitInstruction. Each of the instructions is converted to a "real" PowerPC instruction. When a TOC entry needs to be created, this is done here in the same manner as for the existing LDtoc, LDtocJTI, and LDtocCPT pseudo-instructions (I factored out a new routine to handle this). I had originally thought that if a TOC entry was needed for LDtocL or ADDItocL, it would already have been generated for the previous ADDIStocHA. However, at higher optimization levels, the ADDIStocHA may appear in a different block, which may be assembled textually following the block containing the LDtocL or ADDItocL. So it is necessary to include the possibility of creating a new TOC entry for those two instructions. Note that for LDtocL, we generate a new form of LD called LDrs. This allows specifying the @toc@l relocation for the offset field of the LD instruction (i.e., the offset is replaced by a SymbolLo relocation). When the peephole optimization described above is added, we will need to do similar things for all immediate-form load and store operations. The seven "mcm-n.ll" test cases are kept separate because otherwise the intermingling of various TOC entries and so forth makes the tests fragile and hard to understand. The above assumes use of an external assembler. For use of the integrated assembler, new relocations are added and used by PPCELFObjectWriter. Testing is done with "mcm-obj.ll", which tests for proper generation of the various relocations for the same sequences tested with the external assembler. llvm-svn: 168708
* Remove the dependent libraries feature.Bill Wendling2012-11-271-8/+0
| | | | | | The dependent libraries feature was never used and has bit-rotted. Remove it. llvm-svn: 168694
* [arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier2012-11-271-4/+10
| | | | | | | | classes. The associated test case still doesn't pass, but it does have far fewer issues. rdar://12719844 llvm-svn: 168657
* Remove the X86 Maximal Stack Alignment Check pass as it is no longer necessary.Chad Rosier2012-11-263-50/+0
| | | | | | | | | | | | | | | This pass was conservative in that it always reserved the FP to enable dynamic stack realignment, which allowed the RA to use aligned spills for vector registers. This happens even when spills were not necessary. The RA has since been improved to use unaligned spills when necessary. The new behavior is to realign the stack if the frame pointer was already reserved for some other reason, but don't reserve the frame pointer just because a function contains vector virtual registers. Part of rdar://12719844 llvm-svn: 168627
* Fix comments in HexagonOperands.td.Jyotsna Verma2012-11-261-29/+27
| | | | llvm-svn: 168617
* Normalize splat 256bit vectors with 8 elements.Jakub Staszak2012-11-261-1/+1
| | | | llvm-svn: 168600
* Decouple MCInstBuilder from the streamer per Eli's request.Benjamin Kramer2012-11-263-156/+111
| | | | llvm-svn: 168597
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