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* [SEH] Emit 32-bit SEH tables for the new EH IRReid Kleckner2015-09-092-19/+54
| | | | | | | | | | | The 32-bit tables don't actually contain PC range data, so emitting them is incredibly simple. The 64-bit tables, on the other hand, use the same table for state numbering as well as label ranges. This makes things more difficult, so it will be implemented later. llvm-svn: 247192
* Revert "AVX512: Implemented encoding and intrinsics for vextracti64x4 ↵Renato Golin2015-09-091-109/+52
| | | | | | | | ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding." This reverts commit r247149, as it was breaking numerous buildbots of varied architectures. llvm-svn: 247177
* Save LaneMask with livein registersMatthias Braun2015-09-096-21/+19
| | | | | | | | | | | | | | | | | With subregister liveness enabled we can detect the case where only parts of a register are live in, this is expressed as a 32bit lanemask. The current code only keeps registers in the live-in list and therefore enumerated all subregisters affected by the lanemask. This turned out to be too conservative as the subregister may also cover additional parts of the lanemask which are not live. Expressing a given lanemask by enumerating a minimum set of subregisters is computationally expensive so the best solution is to simply change the live-in list to store the lanemasks as well. This will reduce memory usage for targets using subregister liveness and slightly increase it for other targets Differential Revision: http://reviews.llvm.org/D12442 llvm-svn: 247171
* [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatibleChandler Carruth2015-09-092-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | with the new pass manager, and no longer relying on analysis groups. This builds essentially a ground-up new AA infrastructure stack for LLVM. The core ideas are the same that are used throughout the new pass manager: type erased polymorphism and direct composition. The design is as follows: - FunctionAAResults is a type-erasing alias analysis results aggregation interface to walk a single query across a range of results from different alias analyses. Currently this is function-specific as we always assume that aliasing queries are *within* a function. - AAResultBase is a CRTP utility providing stub implementations of various parts of the alias analysis result concept, notably in several cases in terms of other more general parts of the interface. This can be used to implement only a narrow part of the interface rather than the entire interface. This isn't really ideal, this logic should be hoisted into FunctionAAResults as currently it will cause a significant amount of redundant work, but it faithfully models the behavior of the prior infrastructure. - All the alias analysis passes are ported to be wrapper passes for the legacy PM and new-style analysis passes for the new PM with a shared result object. In some cases (most notably CFL), this is an extremely naive approach that we should revisit when we can specialize for the new pass manager. - BasicAA has been restructured to reflect that it is much more fundamentally a function analysis because it uses dominator trees and loop info that need to be constructed for each function. All of the references to getting alias analysis results have been updated to use the new aggregation interface. All the preservation and other pass management code has been updated accordingly. The way the FunctionAAResultsWrapperPass works is to detect the available alias analyses when run, and add them to the results object. This means that we should be able to continue to respect when various passes are added to the pipeline, for example adding CFL or adding TBAA passes should just cause their results to be available and to get folded into this. The exception to this rule is BasicAA which really needs to be a function pass due to using dominator trees and loop info. As a consequence, the FunctionAAResultsWrapperPass directly depends on BasicAA and always includes it in the aggregation. This has significant implications for preserving analyses. Generally, most passes shouldn't bother preserving FunctionAAResultsWrapperPass because rebuilding the results just updates the set of known AA passes. The exception to this rule are LoopPass instances which need to preserve all the function analyses that the loop pass manager will end up needing. This means preserving both BasicAAWrapperPass and the aggregating FunctionAAResultsWrapperPass. Now, when preserving an alias analysis, you do so by directly preserving that analysis. This is only necessary for non-immutable-pass-provided alias analyses though, and there are only three of interest: BasicAA, GlobalsAA (formerly GlobalsModRef), and SCEVAA. Usually BasicAA is preserved when needed because it (like DominatorTree and LoopInfo) is marked as a CFG-only pass. I've expanded GlobalsAA into the preserved set everywhere we previously were preserving all of AliasAnalysis, and I've added SCEVAA in the intersection of that with where we preserve SCEV itself. One significant challenge to all of this is that the CGSCC passes were actually using the alias analysis implementations by taking advantage of a pretty amazing set of loop holes in the old pass manager's analysis management code which allowed analysis groups to slide through in many cases. Moving away from analysis groups makes this problem much more obvious. To fix it, I've leveraged the flexibility the design of the new PM components provides to just directly construct the relevant alias analyses for the relevant functions in the IPO passes that need them. This is a bit hacky, but should go away with the new pass manager, and is already in many ways cleaner than the prior state. Another significant challenge is that various facilities of the old alias analysis infrastructure just don't fit any more. The most significant of these is the alias analysis 'counter' pass. That pass relied on the ability to snoop on AA queries at different points in the analysis group chain. Instead, I'm planning to build printing functionality directly into the aggregation layer. I've not included that in this patch merely to keep it smaller. Note that all of this needs a nearly complete rewrite of the AA documentation. I'm planning to do that, but I'd like to make sure the new design settles, and to flesh out a bit more of what it looks like in the new pass manager first. Differential Revision: http://reviews.llvm.org/D12080 llvm-svn: 247167
* AMDGPU: Extract full 64-bit subregister and use subregsMatt Arsenault2015-09-091-35/+29
| | | | | | | | | | | | Instead of extracting both 32-bit components from the 128-bit register. This produces fewer copies and is easier for the copy peephole optimizer to understand and see the actual uses as extracts from a reg_sequence. This avoids needing to handle subregister composing in the PeepholeOptimizer's ValueTracker for this case. llvm-svn: 247162
* AMDGPU: Remove unused multiclass argumentMatt Arsenault2015-09-091-5/+4
| | | | llvm-svn: 247161
* [WebAssembly] Implement calls with void return types.Dan Gohman2015-09-094-8/+17
| | | | llvm-svn: 247158
* AMDGPU/SI: Fold operands through REG_SEQUENCE instructionsTom Stellard2015-09-091-0/+21
| | | | | | | | | | | | | | Summary: This helps mostly when we use add instructions for address calculations that contain immediates. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D12256 llvm-svn: 247157
* [CostModel][AArch64] Remove amortization factor for some of the vector ↵Silviu Baranga2015-09-091-4/+5
| | | | | | | | | | | | | | | | | select instructions Summary: We are not scalarizing the wide selects in codegen for i16 and i32 and therefore we can remove the amortization factor. We still have issues with i64 vectors in codegen though. Reviewers: mcrosier Subscribers: mcrosier, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D12724 llvm-svn: 247156
* [WebAssembly] Tidy up some unneeded newline characters.Dan Gohman2015-09-091-10/+9
| | | | llvm-svn: 247152
* AVX512: Implemented encoding and intrinsics forIgor Breger2015-09-091-52/+109
| | | | | | | | | vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11802 llvm-svn: 247149
* [mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and ↵Zoran Jovanovic2015-09-095-11/+120
| | | | | | | | SRL16 instructions Differential Revision: http://reviews.llvm.org/D11178 llvm-svn: 247146
* [mips][microMIPS] Implement CACHEE and PREFE instructionsZoran Jovanovic2015-09-094-8/+53
| | | | | | Differential Revision: http://reviews.llvm.org/D11628 llvm-svn: 247125
* AMDGPU: Fix not encoding src2 of VOP3b instructionsMatt Arsenault2015-09-091-4/+4
| | | | | | | Broken by r247074. Should include an assembler test, but the assembler is currently broken for VOP3b apparently. llvm-svn: 247123
* [WebAssembly] Fix lowering of calls with more than one argument.Dan Gohman2015-09-091-2/+5
| | | | llvm-svn: 247118
* SelectionDAG: Support Expand of f16 extloadsMatt Arsenault2015-09-091-29/+3
| | | | | | | | | | Currently this hits an assert that extload should always be supported, which assumes integer extloads. This moves a hack out of SI's argument lowering and is covered by existing tests. llvm-svn: 247113
* [WebAssembly] Implement WebAssemblyInstrInfo::copyPhysRegDan Gohman2015-09-093-22/+38
| | | | llvm-svn: 247110
* [WinEH] Emit prologues and epilogues for funcletsReid Kleckner2015-09-085-13/+154
| | | | | | | | | | | | | | | | | | | | | | | | Summary: 32-bit funclets have short prologues that allocate enough stack for the largest call in the whole function. The runtime saves CSRs for the funclet. It doesn't restore CSRs after we finally transfer control back to the parent funciton via a CATCHRET, but that's a separate issue. 32-bit funclets also have to adjust the incoming EBP value, which is what llvm.x86.seh.recoverframe does in the old model. 64-bit funclets need to spill CSRs as normal. For simplicity, this just spills the same set of CSRs as the parent function, rather than trying to compute different CSR sets for the parent function and each funclet. 64-bit funclets also allocate enough stack space for the largest outgoing call frame, like 32-bit. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12546 llvm-svn: 247092
* Fix the PPC CTR Loop pass to look for calls to the intrinsics thatEric Christopher2015-09-081-0/+6
| | | | | | read CTR and count them as reading the CTR. llvm-svn: 247083
* AMDGPU/SI: Fix input vcc operand for VOP2b instructionsMatt Arsenault2015-09-084-41/+57
| | | | | | | | | Adds vcc to output string input for e32. Allows option of using e64 encoding with assembler. Also fixes these instructions not implicitly reading exec. llvm-svn: 247074
* [NVPTX] Added run NVVMReflect pass to NVPTX back-end.Artem Belevich2015-09-081-0/+1
| | | | | | | | | The pass is needed to remove __nvvm_reflect calls when we link in libdevice bitcode that comes with CUDA. Differential Revision: http://reviews.llvm.org/D11663 llvm-svn: 247072
* x32. Fixes a bug in how struct va_list is initialized in x32Derek Schuff2015-09-081-3/+4
| | | | | | | | | | | | | Summary: This patch modifies X86TargetLowering::LowerVASTART so that struct va_list is initialized with 32 bit pointers in x32. It also includes tests that call @llvm.va_start() for x32. Patch by João Porto Subscribers: llvm-commits, hjl.tools Differential Revision: http://reviews.llvm.org/D12346 llvm-svn: 247069
* [WebAssembly] Support running without a register allocator in the default ↵Dan Gohman2015-09-081-35/+0
| | | | | | | | | | | | | CodeGen passes This allows backends which don't use a traditional register allocator, but do need PHI lowering and other passes, to use the default TargetPassConfig::addFastRegAlloc and TargetPassConfig::addOptimizedRegAlloc implementations. Differential Revision: http://reviews.llvm.org/D12691 llvm-svn: 247065
* AMDGPU: Mark s_barrier as a high latency instructionMatt Arsenault2015-09-082-0/+3
| | | | | | | | | | | These were marked as WriteSALU, which is low latency. I'm guessing at the value to use, but it should probably be considered the highest latency instruction. I'm not sure this has any actual effect since hasSideEffects probably is preventing any moving of these. llvm-svn: 247060
* AMDGPU: Fix s_barrier flagsMatt Arsenault2015-09-081-2/+1
| | | | | | | | This should be convergent. This is not a barrier in the isBarrier sense, nor hasCtrlDep. llvm-svn: 247059
* x32. Fixes a bug in i8mem_NOREX declaration.Derek Schuff2015-09-082-6/+17
| | | | | | | | | | | | | | The old implementation assumed LP64 which is broken for x32. Specifically, the MOVE8rm_NOREX and MOVE8mr_NOREX, when selected, would cause a 'Cannot emit physreg copy instruction' error message to be reported. This patch also enable the h-register*ll tests for x32. Differential Revision: http://reviews.llvm.org/D12336 Patch by João Porto llvm-svn: 247058
* AMDGPU: Handle sub of constant for DS offset foldingMatt Arsenault2015-09-081-11/+62
| | | | | | | | | sub C, x - > add (sub 0, x), C for DS offsets. This is mostly to fix regressions that show up when SeparateConstOffsetFromGEP is enabled. llvm-svn: 247054
* Fix CPP Backend for GEP API changes for opaque pointer typesDavid Blaikie2015-09-081-15/+10
| | | | | | Based on a patch by Jerome Witmann. llvm-svn: 247047
* Fix for bz24500: Avoid non-deterministic code generation triggered by the ↵Andrew Kaylor2015-09-081-22/+25
| | | | | | | | | | x86 call frame optimization Patch by Dave Kreitzer Differential Revision: http://reviews.llvm.org/D12620 llvm-svn: 247042
* WebAssembly: NFC rename shr/sarJF Bastien2015-09-081-2/+2
| | | | | | Renamed from: https://github.com/WebAssembly/design/pull/332 llvm-svn: 247028
* Remove white space (test commit)Jun Bum Lim2015-09-081-1/+1
| | | | llvm-svn: 247021
* [mips][microMIPS] Implement LLE, LUI, LW and LWE instructionsZoran Jovanovic2015-09-083-1/+84
| | | | | | Differential Revision: http://reviews.llvm.org/D1179 llvm-svn: 247017
* AVX512: kunpck encoding implementation Igor Breger2015-09-082-17/+17
| | | | | | | | Added tests for encoding. Differential Revision: http://reviews.llvm.org/D12061 llvm-svn: 247010
* [WebAssembly] Enable SSA lowering and other pre-regalloc passesDan Gohman2015-09-081-1/+21
| | | | llvm-svn: 247008
* Removed an old comment, NFCElena Demikhovsky2015-09-081-2/+0
| | | | llvm-svn: 247006
* [mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructionsZoran Jovanovic2015-09-086-2/+109
| | | | | | Differential Revision: http://reviews.llvm.org/D11801 llvm-svn: 246999
* [mips] Reserve address spaces 1-255 for software use.Daniel Sanders2015-09-081-0/+8
| | | | | | | | | | | | Summary: And define them to have noop casts with address spaces 0-255. Reviewers: pekka.jaaskelainen Subscribers: pekka.jaaskelainen, llvm-commits Differential Revision: http://reviews.llvm.org/D12678 llvm-svn: 246990
* [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing ↵Zoran Jovanovic2015-09-082-2/+4
| | | | | | | | 16-bit LBU16, LHU16, LW16, LWGP and LWSP instructions Differential Revision: http://reviews.llvm.org/D10956 llvm-svn: 246987
* compilation issue, NFCElena Demikhovsky2015-09-081-3/+3
| | | | llvm-svn: 246983
* fixed compilation issue, NFC.Elena Demikhovsky2015-09-081-3/+3
| | | | llvm-svn: 246982
* AVX-512: Lowering for 512-bit vector shuffles.Elena Demikhovsky2015-09-084-68/+324
| | | | | | | | Vector types: <8 x 64>, <16 x 32>, <32 x 16> float and integer. Differential Revision: http://reviews.llvm.org/D10683 llvm-svn: 246981
* [mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL.W.fmt, FLOOR.L.fmt, ↵Zoran Jovanovic2015-09-074-12/+155
| | | | | | | | FLOOR.W.fmt, TRUNC.L.fmt, TRUNC.W.fmt, RSQRT.fmt and SQRT.fmt instructions Differential Revision: http://reviews.llvm.org/D11674 llvm-svn: 246968
* [mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructionsZoran Jovanovic2015-09-076-10/+94
| | | | | | Differential Revision: http://reviews.llvm.org/D11181 llvm-svn: 246963
* [ARM] Get rid of SelectT2ShifterOperandReg, NFCJohn Brawn2015-09-072-26/+2
| | | | | | | | | SelectT2ShifterOperandReg has identical behaviour to SelectImmShifterOperand, so get rid of it and use SelectImmShifterOperand instead. Differential Revision: http://reviews.llvm.org/D12195 llvm-svn: 246962
* [mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, ↵Zoran Jovanovic2015-09-074-58/+290
| | | | | | | | MAX.fmt, MIN.fmt, MAXA.fmt, MINA.fmt and CMP.condn.fmt instructions Differential Revision: http://reviews.llvm.org/D12141 llvm-svn: 246960
* Prune utf8 chars in comments.NAKAMURA Takumi2015-09-071-2/+2
| | | | llvm-svn: 246953
* [PowerPC] Don't commute trivial rlwimi instructionsHal Finkel2015-09-061-0/+5
| | | | | | | | | | | | | | | To commute a trivial rlwimi instructions (meaning one with a full mask and zero shift), we'd need to ability to form an all-zero mask (instead of an all-one mask) using rlwimi. We can't represent this, however, and we'll miscompile code if we try. The code quality problem that this highlights (that SDAG simplification can lead to us generating an ISD::OR node with a constant zero LHS) will be fixed as a follow-up. Fixes PR24719. llvm-svn: 246937
* [mips][microMIPS] Implement ADD.fmt, SUB.fmt, MOV.fmt, MUL.fmt, DIV.fmt, ↵Zoran Jovanovic2015-09-053-4/+159
| | | | | | | | MADDF.fmt, MSUBF.fmt and NEG.fmt instructions Differential Revision: http://reviews.llvm.org/D11978 llvm-svn: 246919
* [PowerPC] Fix and(or(x, c1), c2) -> rlwimi generationHal Finkel2015-09-051-3/+15
| | | | | | | | | | | | | | | | PPCISelDAGToDAG has a transformation that generates a rlwimi instruction from an input pattern that looks like this: and(or(x, c1), c2) but the associated logic does not work if there are bits that are 1 in c1 but 0 in c2 (these are normally canonicalized away, but that can't happen if the 'or' has other users. Make sure we abort the transformation if such bits are discovered. Fixes PR24704. llvm-svn: 246900
* [PowerPC] Enable interleaved-access vectorizationHal Finkel2015-09-042-1/+43
| | | | | | | | | | | This adds a basic cost model for interleaved-access vectorization (and a better default for shuffles), and enables interleaved-access vectorization by default. The relevant difference from the default cost model for interleaved-access vectorization, is that on PPC, the shuffles that end up being used are *much* cheaper than modeling the process with insert/extract pairs (which are quite expensive, especially on older cores). llvm-svn: 246824
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